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| author | Olivier Martin <olivier.martin@arm.com> | 2013-07-17 06:25:15 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2013-07-17 06:25:15 +0000 |
| commit | a1cca63885be79ca4c50f3b191fd4edda902712d (patch) | |
| tree | e4d5813f11cde018106dc89c0055167512d2ba03 /ArmPkg | |
| parent | 0b342ffb76c320e56c72eeed3d877415659c252b (diff) | |
| download | edk2-a1cca63885be79ca4c50f3b191fd4edda902712d.tar.gz edk2-a1cca63885be79ca4c50f3b191fd4edda902712d.tar.bz2 edk2-a1cca63885be79ca4c50f3b191fd4edda902712d.zip | |
ArmPkg/PL390Gic: Populate the GIC Distributor Target Register with the GIC CPU ID retrieved from the GIC
The GIC CPU Id (the GIC CPU interface the CPU is connected to) can be retrieved by reading the first
registers of the GIC CPU Target Registers.
The first GIC Distributor Target registers correspond to the SGIs.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14479 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg')
| -rw-r--r-- | ArmPkg/Drivers/PL390Gic/PL390GicDxe.c | 25 |
1 files changed, 20 insertions, 5 deletions
diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c b/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c index 31e91f9c34..310053afe0 100644 --- a/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c +++ b/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c @@ -371,11 +371,26 @@ InterruptDxeInitialize ( );
}
- // Configure interrupts for Primary Cpu
- CpuTarget = (1 << PcdGet32 (PcdGicPrimaryCoreId));
- CpuTarget |= (CpuTarget << 24) | (CpuTarget << 16) | (CpuTarget << 8);
- for (Index = 0; Index < (mGicNumInterrupts / 4); Index++) {
- MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index*4), CpuTarget);
+ //
+ // Targets the interrupts to the Primary Cpu
+ //
+
+ // Only Primary CPU will run this code. We can identify our GIC CPU ID by reading
+ // the GIC Distributor Target register. The 8 first GICD_ITARGETSRn are banked to each
+ // connected CPU. These 8 registers hold the CPU targets fields for interrupts 0-31.
+ // More Info in the GIC Specification about "Interrupt Processor Targets Registers"
+ //
+ // Read the first Interrupt Processor Targets Register (that corresponds to the 4
+ // first SGIs)
+ CpuTarget = MmioRead32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR);
+
+ // The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value
+ // cannot be 0.
+ ASSERT (CpuTarget != 0);
+
+ // The 8 first Interrupt Processor Targets Registers are read-only
+ for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
+ MmioWrite32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);
}
// Set binary point reg to 0x7 (no preemption)
|