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| author | Olivier Martin <olivier.martin@arm.com> | 2013-08-21 12:05:44 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2013-08-21 12:05:44 +0000 |
| commit | cc9355448601a16089b633ebb0a9d01086e5c91f (patch) | |
| tree | 62df6445b78b6ebc58d46f7e0529c39946184a5f /ArmPkg | |
| parent | a639401d2fb4fccc7830065e74c8782700035adf (diff) | |
| download | edk2-cc9355448601a16089b633ebb0a9d01086e5c91f.tar.gz edk2-cc9355448601a16089b633ebb0a9d01086e5c91f.tar.bz2 edk2-cc9355448601a16089b633ebb0a9d01086e5c91f.zip | |
ArmPlatformPkg/Sec: Remove SCR and CPTR initialization from SetupExceptionLevel3
This is already taken care by Sec when PcdTrustzoneSupport = TRUE.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14580 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg')
| -rw-r--r-- | ArmPkg/ArmPkg.dec | 58 |
1 files changed, 40 insertions, 18 deletions
diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec index 39f264251b..0f094c12a2 100644 --- a/ArmPkg/ArmPkg.dec +++ b/ArmPkg/ArmPkg.dec @@ -110,24 +110,6 @@ gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
-
- #
- # ARM Security Extension
- #
-
- # Secure Configuration Register
- # - BIT0 : NS - Non Secure bit
- # - BIT1 : IRQ Handler
- # - BIT2 : FIQ Handler
- # - BIT3 : EA - External Abort
- # - BIT4 : FW - F bit writable
- # - BIT5 : AW - A bit writable
- # - BIT6 : nET - Not Early Termination
- # - BIT7 : SCD - Secure Monitor Call Disable
- # - BIT8 : HCE - Hyp Call enable
- # - BIT9 : SIF - Secure Instruction Fetch
- # 0x31 = NS | EA | FW
- gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
# System Memory (DRAM): These PCDs define the region of in-built system memory
# Some platforms can get DRAM extensions, these additional regions will be declared
@@ -161,6 +143,24 @@ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
[PcdsFixedAtBuild.ARM]
+ #
+ # ARM Security Extension
+ #
+
+ # Secure Configuration Register
+ # - BIT0 : NS - Non Secure bit
+ # - BIT1 : IRQ Handler
+ # - BIT2 : FIQ Handler
+ # - BIT3 : EA - External Abort
+ # - BIT4 : FW - F bit writable
+ # - BIT5 : AW - A bit writable
+ # - BIT6 : nET - Not Early Termination
+ # - BIT7 : SCD - Secure Monitor Call Disable
+ # - BIT8 : HCE - Hyp Call enable
+ # - BIT9 : SIF - Secure Instruction Fetch
+ # 0x31 = NS | EA | FW
+ gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
+
# By default we do not do a transition to non-secure mode
gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
@@ -183,6 +183,28 @@ gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
[PcdsFixedAtBuild.AARCH64]
+ #
+ # AArch64 Security Extension
+ #
+
+ # Secure Configuration Register
+ # - BIT0 : NS - Non Secure bit
+ # - BIT1 : IRQ Handler
+ # - BIT2 : FIQ Handler
+ # - BIT3 : EA - External Abort
+ # - BIT4 : FW - F bit writable
+ # - BIT5 : AW - A bit writable
+ # - BIT6 : nET - Not Early Termination
+ # - BIT7 : SCD - Secure Monitor Call Disable
+ # - BIT8 : HCE - Hyp Call enable
+ # - BIT9 : SIF - Secure Instruction Fetch
+ # - BIT10: RW - Register width control for lower exception levels
+ # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
+ # - BIT12: TWI - Trap WFI
+ # - BIT13: TWE - Trap WFE
+ # 0x501 = NS | HCE | RW
+ gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
+
# By default we do transition to EL2 non-secure mode with Stack for EL2.
# Mode Description Bits
# NS EL2 SP2 all interupts disabled = 0x3c9
|