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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-04-06 14:05:12 +0100 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-04-06 21:31:48 +0100 |
| commit | 1344c8c6052c18744e914d0016f94d792f111604 (patch) | |
| tree | 82bd22916d6c08518c7484424189860bcddce26b /ArmPlatformPkg/ArmVExpressPkg/Include | |
| parent | 7c410b3d4180087020c7734bf67cdc4ad9fdb136 (diff) | |
| download | edk2-1344c8c6052c18744e914d0016f94d792f111604.tar.gz edk2-1344c8c6052c18744e914d0016f94d792f111604.tar.bz2 edk2-1344c8c6052c18744e914d0016f94d792f111604.zip | |
ArmPlatformPkg/FVP: map motherboard VRAM as uncached memory
The VRAM of the PL111 on the FVP Base/Foundation models is described as
device memory rather than uncached memory, which is not an accurate
description of the nature of the region (i.e., a framebuffer), and may
result in problems when using accelerated string routines to access the
region, since this may legally involve unaligned accesses or DC ZVA
instructions, which are not allowed on device mappings.
So split of the 8 MB VRAM region into a separate region, and map it using
memory attributes.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'ArmPlatformPkg/ArmVExpressPkg/Include')
| -rw-r--r-- | ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h index 06414e6e72..d856b6daa1 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h +++ b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h @@ -40,9 +40,11 @@ #define ARM_VE_SMB_SRAM_BASE 0x2E000000
#define ARM_VE_SMB_SRAM_SZ SIZE_64KB
// USB, Ethernet, VRAM
-#define ARM_VE_SMB_PERIPH_BASE 0x18000000
-#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE
-#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB
+#define ARM_VE_SMB_PERIPH_BASE 0x18800000
+#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB - SIZE_8MB)
+
+#define PL111_CLCD_VRAM_MOTHERBOARD_BASE 0x18000000
+#define PL111_CLCD_VRAM_MOTHERBOARD_SIZE 0x800000
// DRAM
#define ARM_VE_DRAM_BASE PcdGet64 (PcdSystemMemoryBase)
@@ -74,7 +76,4 @@ #define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1
#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1
-// VRAM offset for the PL111 Colour LCD Controller on the motherboard
-#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)
-
#endif
|