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| author | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2013-03-12 00:43:58 +0000 |
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| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2013-03-12 00:43:58 +0000 |
| commit | 9f5c60c38b953c9890b7bd9ab35d6bf2c530d3bb (patch) | |
| tree | 5a256b825748054ec7dadddfc6029c6d2c852869 /ArmPlatformPkg/ArmVExpressPkg/Include | |
| parent | c0b2e4775dcb06d9016f17f5d22e6276d9b58397 (diff) | |
| download | edk2-9f5c60c38b953c9890b7bd9ab35d6bf2c530d3bb.tar.gz edk2-9f5c60c38b953c9890b7bd9ab35d6bf2c530d3bb.tar.bz2 edk2-9f5c60c38b953c9890b7bd9ab35d6bf2c530d3bb.zip | |
ArmPlatformPkg/CTA15-A7: Add a convenient way to restore default values in NOR flash.
Setting bit4 of SCC register 48 now triggers the erasing of the memory region
reserved for variable storage in NOR flash and the restoration of the default
headers in flash.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14177 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPlatformPkg/ArmVExpressPkg/Include')
| -rw-r--r-- | ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15-A7/ArmPlatform.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15-A7/ArmPlatform.h b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15-A7/ArmPlatform.h index 365f06002b..b52f89a5cb 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15-A7/ArmPlatform.h +++ b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15-A7/ArmPlatform.h @@ -97,10 +97,11 @@ #define ARM_CTA15A7_SCC_SYSINFO ARM_CTA15A7_SCC_CFGREG48
-#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A7_NUM_CPU(val) (((val) >> 20) & 0xF)
-#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A15_NUM_CPU(val) (((val) >> 16) & 0xF)
-#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A15 (1 << 0)
-#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A7 (1 << 1)
+#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A7_NUM_CPU(val) (((val) >> 20) & 0xF)
+#define ARM_CTA15A7_SCC_SYSINFO_CLUSTER_A15_NUM_CPU(val) (((val) >> 16) & 0xF)
+#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A15 (1 << 0)
+#define ARM_CTA15A7_SCC_SYSINFO_ACTIVE_CLUSTER_A7 (1 << 1)
+#define ARM_CTA15A7_SCC_SYSINFO_UEFI_RESTORE_DEFAULT_NORFLASH (1 << 4)
#define ARM_CTA15A7_SPC_BASE 0x7FFF0B00
#define ARM_CTA15A7_SPC_WAKE_INT_MASK (ARM_CTA15A7_SPC_BASE + 0x24)
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