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| author | Michael Kubacki <michael.kubacki@microsoft.com> | 2021-12-05 14:53:52 -0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-12-07 17:24:28 +0000 |
| commit | 40b0b23ed34f48c26d711d3e4613a4bb35eeadff (patch) | |
| tree | aba2ec9c8c50e4deb9486a16297ba496c4a302d2 /ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.h | |
| parent | 429309e0c6b74792d679681a8edd0d5ae0ff850c (diff) | |
| download | edk2-40b0b23ed34f48c26d711d3e4613a4bb35eeadff.tar.gz edk2-40b0b23ed34f48c26d711d3e4613a4bb35eeadff.tar.bz2 edk2-40b0b23ed34f48c26d711d3e4613a4bb35eeadff.zip | |
ArmPlatformPkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737
Apply uncrustify changes to .c/.h files in the ArmPlatformPkg package
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Andrew Fish <afish@apple.com>
Diffstat (limited to 'ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.h')
| -rw-r--r-- | ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.h | 51 |
1 files changed, 25 insertions, 26 deletions
diff --git a/ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.h b/ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.h index 57f56f7d37..42d87a16a3 100644 --- a/ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.h +++ b/ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.h @@ -6,38 +6,37 @@ **/
-
#ifndef __PL061_GPIO_H__
#define __PL061_GPIO_H__
#include <Protocol/EmbeddedGpio.h>
// PL061 GPIO Registers
-#define PL061_GPIO_DATA_REG_OFFSET ((UINTN) 0x000)
-#define PL061_GPIO_DATA_REG 0x000
-#define PL061_GPIO_DIR_REG 0x400
-#define PL061_GPIO_IS_REG 0x404
-#define PL061_GPIO_IBE_REG 0x408
-#define PL061_GPIO_IEV_REG 0x40C
-#define PL061_GPIO_IE_REG 0x410
-#define PL061_GPIO_RIS_REG 0x414
-#define PL061_GPIO_MIS_REG 0x410
-#define PL061_GPIO_IC_REG 0x41C
-#define PL061_GPIO_AFSEL_REG 0x420
-
-#define PL061_GPIO_PERIPH_ID0 0xFE0
-#define PL061_GPIO_PERIPH_ID1 0xFE4
-#define PL061_GPIO_PERIPH_ID2 0xFE8
-#define PL061_GPIO_PERIPH_ID3 0xFEC
-
-#define PL061_GPIO_PCELL_ID0 0xFF0
-#define PL061_GPIO_PCELL_ID1 0xFF4
-#define PL061_GPIO_PCELL_ID2 0xFF8
-#define PL061_GPIO_PCELL_ID3 0xFFC
-
-#define PL061_GPIO_PINS 8
+#define PL061_GPIO_DATA_REG_OFFSET ((UINTN) 0x000)
+#define PL061_GPIO_DATA_REG 0x000
+#define PL061_GPIO_DIR_REG 0x400
+#define PL061_GPIO_IS_REG 0x404
+#define PL061_GPIO_IBE_REG 0x408
+#define PL061_GPIO_IEV_REG 0x40C
+#define PL061_GPIO_IE_REG 0x410
+#define PL061_GPIO_RIS_REG 0x414
+#define PL061_GPIO_MIS_REG 0x410
+#define PL061_GPIO_IC_REG 0x41C
+#define PL061_GPIO_AFSEL_REG 0x420
+
+#define PL061_GPIO_PERIPH_ID0 0xFE0
+#define PL061_GPIO_PERIPH_ID1 0xFE4
+#define PL061_GPIO_PERIPH_ID2 0xFE8
+#define PL061_GPIO_PERIPH_ID3 0xFEC
+
+#define PL061_GPIO_PCELL_ID0 0xFF0
+#define PL061_GPIO_PCELL_ID1 0xFF4
+#define PL061_GPIO_PCELL_ID2 0xFF8
+#define PL061_GPIO_PCELL_ID3 0xFFC
+
+#define PL061_GPIO_PINS 8
// All bits low except one bit high, native bit length
-#define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin)))
+#define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin)))
-#endif // __PL061_GPIO_H__
+#endif // __PL061_GPIO_H__
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