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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-12-04 21:57:55 +0000 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-12-08 16:30:32 +0000 |
| commit | eb618ba42fe07f0b710f68ba6017cee006a0b0ec (patch) | |
| tree | 8ff699caff4807bb24ff53e9c3a2f036b5819490 /ArmPlatformPkg/Drivers | |
| parent | d9b53608607b0c5df0031f18486b3c0fa8a1fb6e (diff) | |
| download | edk2-eb618ba42fe07f0b710f68ba6017cee006a0b0ec.tar.gz edk2-eb618ba42fe07f0b710f68ba6017cee006a0b0ec.tar.bz2 edk2-eb618ba42fe07f0b710f68ba6017cee006a0b0ec.zip | |
ArmPlatformPkg/LcdGraphicsOutputDxe: move headers into driver directory
The HdLcd.h and PL111Lcd.h header files are internal headers that should
not be used by other drivers. So move them from Include/Drivers into the
driver directory instead.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'ArmPlatformPkg/Drivers')
4 files changed, 240 insertions, 4 deletions
diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c index 2bfe2c0fe2..f5d7b53905 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c @@ -18,8 +18,7 @@ #include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
-#include <Drivers/HdLcd.h>
-
+#include "HdLcd.h"
#include "LcdGraphicsOutputDxe.h"
/**********************************************************************
diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.h b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.h new file mode 100644 index 0000000000..6df97a9dfe --- /dev/null +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.h @@ -0,0 +1,89 @@ +/** @file HDLcd.h
+
+ Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ **/
+
+#ifndef _HDLCD_H_
+#define _HDLCD_H_
+
+//
+// HDLCD Controller Register Offsets
+//
+
+#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)
+#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)
+#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)
+#define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)
+#define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)
+#define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)
+#define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)
+#define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)
+#define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)
+#define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)
+#define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)
+#define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)
+#define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)
+#define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)
+#define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)
+#define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)
+#define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)
+#define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)
+#define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)
+#define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)
+#define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)
+#define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)
+#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)
+#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)
+
+
+//
+// HDLCD Values of registers
+//
+
+// HDLCD Interrupt mask, clear and status register
+#define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */
+#define HDLCD_BUS_ERROR BIT1 /* DMA bus error */
+#define HDLCD_SYNC BIT2 /* Vertical sync */
+#define HDLCD_UNDERRUN BIT3 /* No Data available while DATAEN active */
+
+// CLCD_CONTROL Control register
+#define HDLCD_DISABLE 0
+#define HDLCD_ENABLE BIT0
+
+// Bus Options
+#define HDLCD_BURST_1 BIT0
+#define HDLCD_BURST_2 BIT1
+#define HDLCD_BURST_4 BIT2
+#define HDLCD_BURST_8 BIT3
+#define HDLCD_BURST_16 BIT4
+
+// Polarities - HIGH
+#define HDLCD_VSYNC_HIGH BIT0
+#define HDLCD_HSYNC_HIGH BIT1
+#define HDLCD_DATEN_HIGH BIT2
+#define HDLCD_DATA_HIGH BIT3
+#define HDLCD_PXCLK_HIGH BIT4
+// Polarities - LOW (for completion and for ease of understanding the hardware settings)
+#define HDLCD_VSYNC_LOW 0
+#define HDLCD_HSYNC_LOW 0
+#define HDLCD_DATEN_LOW 0
+#define HDLCD_DATA_LOW 0
+#define HDLCD_PXCLK_LOW 0
+
+// Pixel Format
+#define HDLCD_LITTLE_ENDIAN (0 << 31)
+#define HDLCD_BIG_ENDIAN (1 << 31)
+
+// Number of bytes per pixel
+#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3)
+
+#endif /* _HDLCD_H_ */
diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c index b5e113b844..a9ce60c5b0 100644 --- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c @@ -15,9 +15,8 @@ #include <Library/IoLib.h>
#include <Library/MemoryAllocationLib.h>
-#include <Drivers/PL111Lcd.h>
-
#include "LcdGraphicsOutputDxe.h"
+#include "PL111Lcd.h"
/**********************************************************************
*
diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.h b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.h new file mode 100644 index 0000000000..18e28af805 --- /dev/null +++ b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.h @@ -0,0 +1,149 @@ +/** @file PL111Lcd.h
+
+ Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ **/
+
+#ifndef _PL111LCD_H__
+#define _PL111LCD_H__
+
+/**********************************************************************
+ *
+ * This header file contains all the bits of the PL111 that are
+ * platform independent.
+ *
+ **********************************************************************/
+
+// Controller Register Offsets
+#define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000)
+#define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004)
+#define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008)
+#define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C)
+#define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010)
+#define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014)
+#define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018)
+#define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C)
+#define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020)
+#define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024)
+#define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028)
+#define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C)
+#define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030)
+#define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200)
+
+// Identification Register Offsets
+#define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0)
+#define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4)
+#define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8)
+#define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC)
+#define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0)
+#define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4)
+#define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8)
+#define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC)
+
+#define PL111_CLCD_PERIPH_ID_0 0x11
+#define PL111_CLCD_PERIPH_ID_1 0x11
+#define PL111_CLCD_PERIPH_ID_2 0x04
+#define PL111_CLCD_PERIPH_ID_3 0x00
+#define PL111_CLCD_P_CELL_ID_0 0x0D
+#define PL111_CLCD_P_CELL_ID_1 0xF0
+#define PL111_CLCD_P_CELL_ID_2 0x05
+#define PL111_CLCD_P_CELL_ID_3 0xB1
+
+/**********************************************************************/
+
+// Register components (register bits)
+
+// This should make life easier to program specific settings in the different registers
+// by simplifying the setting up of the individual bits of each register
+// and then assembling the final register value.
+
+/**********************************************************************/
+
+// Register: PL111_REG_LCD_TIMING_0
+#define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2))
+
+// Register: PL111_REG_LCD_TIMING_1
+#define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1))
+
+// Register: PL111_REG_LCD_TIMING_2
+#define PL111_BIT_SHIFT_PCD_HI 27
+#define PL111_BIT_SHIFT_BCD 26
+#define PL111_BIT_SHIFT_CPL 16
+#define PL111_BIT_SHIFT_IOE 14
+#define PL111_BIT_SHIFT_IPC 13
+#define PL111_BIT_SHIFT_IHS 12
+#define PL111_BIT_SHIFT_IVS 11
+#define PL111_BIT_SHIFT_ACB 6
+#define PL111_BIT_SHIFT_CLKSEL 5
+#define PL111_BIT_SHIFT_PCD_LO 0
+
+#define PL111_BCD (1 << 26)
+#define PL111_IPC (1 << 13)
+#define PL111_IHS (1 << 12)
+#define PL111_IVS (1 << 11)
+
+#define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16))
+
+// Register: PL111_REG_LCD_TIMING_3
+#define PL111_BIT_SHIFT_LEE 16
+#define PL111_BIT_SHIFT_LED 0
+
+#define PL111_CTRL_WATERMARK (1 << 16)
+#define PL111_CTRL_LCD_V_COMP (1 << 12)
+#define PL111_CTRL_LCD_PWR (1 << 11)
+#define PL111_CTRL_BEPO (1 << 10)
+#define PL111_CTRL_BEBO (1 << 9)
+#define PL111_CTRL_BGR (1 << 8)
+#define PL111_CTRL_LCD_DUAL (1 << 7)
+#define PL111_CTRL_LCD_MONO_8 (1 << 6)
+#define PL111_CTRL_LCD_TFT (1 << 5)
+#define PL111_CTRL_LCD_BW (1 << 4)
+#define PL111_CTRL_LCD_1BPP (0 << 1)
+#define PL111_CTRL_LCD_2BPP (1 << 1)
+#define PL111_CTRL_LCD_4BPP (2 << 1)
+#define PL111_CTRL_LCD_8BPP (3 << 1)
+#define PL111_CTRL_LCD_16BPP (4 << 1)
+#define PL111_CTRL_LCD_24BPP (5 << 1)
+#define PL111_CTRL_LCD_16BPP_565 (6 << 1)
+#define PL111_CTRL_LCD_12BPP_444 (7 << 1)
+#define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1)
+#define PL111_CTRL_LCD_EN 1
+
+/**********************************************************************/
+
+// Register: PL111_REG_LCD_TIMING_0
+#define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24)
+#define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16)
+#define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8)
+#define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2)
+
+// Register: PL111_REG_LCD_TIMING_1
+#define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24)
+#define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16)
+#define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10)
+#define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC)
+
+// Register: PL111_REG_LCD_TIMING_2
+#define PL111_BIT_MASK_PCD_HI 0xF8000000
+#define PL111_BIT_MASK_BCD 0x04000000
+#define PL111_BIT_MASK_CPL 0x03FF0000
+#define PL111_BIT_MASK_IOE 0x00004000
+#define PL111_BIT_MASK_IPC 0x00002000
+#define PL111_BIT_MASK_IHS 0x00001000
+#define PL111_BIT_MASK_IVS 0x00000800
+#define PL111_BIT_MASK_ACB 0x000007C0
+#define PL111_BIT_MASK_CLKSEL 0x00000020
+#define PL111_BIT_MASK_PCD_LO 0x0000001F
+
+// Register: PL111_REG_LCD_TIMING_3
+#define PL111_BIT_MASK_LEE 0x00010000
+#define PL111_BIT_MASK_LED 0x0000007F
+
+#endif /* _PL111LCD_H__ */
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