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| author | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-07-01 16:33:22 +0000 |
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| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-07-01 16:33:22 +0000 |
| commit | c52e2dca64d90140130444fb647590763b4594ad (patch) | |
| tree | 79bab40fea57b46ec956d6a2344da52b3937b0e2 /ArmPlatformPkg/Include/Drivers | |
| parent | 3c4b742c182785b0e3ae0217a8e3a08b47b5c7a8 (diff) | |
| download | edk2-c52e2dca64d90140130444fb647590763b4594ad.tar.gz edk2-c52e2dca64d90140130444fb647590763b4594ad.tar.bz2 edk2-c52e2dca64d90140130444fb647590763b4594ad.zip | |
ArmPlatformPkg/PL35xSmc: Clean SMC driver to replace hardcoded Chip Select into the driver itself by passing SMC configuration to the driver
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11959 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPlatformPkg/Include/Drivers')
| -rw-r--r-- | ArmPlatformPkg/Include/Drivers/PL35xSmc.h | 90 |
1 files changed, 53 insertions, 37 deletions
diff --git a/ArmPlatformPkg/Include/Drivers/PL35xSmc.h b/ArmPlatformPkg/Include/Drivers/PL35xSmc.h index 0da47f9982..52d64f482b 100644 --- a/ArmPlatformPkg/Include/Drivers/PL35xSmc.h +++ b/ArmPlatformPkg/Include/Drivers/PL35xSmc.h @@ -12,46 +12,62 @@ *
**/
-#ifndef PL354SMC_H_
-#define PL354SMC_H_
+#ifndef PL35xSMC_H_
+#define PL35xSMC_H_
-#define PL354_SMC_DIRECT_CMD_OFFSET 0x10
-#define PL354_SMC_SET_CYCLES_OFFSET 0x14
-#define PL354_SMC_SET_OPMODE_OFFSET 0x18
+#define PL350_SMC_DIRECT_CMD_OFFSET 0x10
+#define PL350_SMC_SET_CYCLES_OFFSET 0x14
+#define PL350_SMC_SET_OPMODE_OFFSET 0x18
-#define PL354_SMC_DIRECT_CMD_ADDR(addr) ((addr) & 0xFFFFF)
-#define PL354_SMC_DIRECT_CMD_ADDR_SET_CRE (1 << 20)
-#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE_UPDATE (3 << 21)
-#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE (2 << 21)
-#define PL354_SMC_DIRECT_CMD_ADDR_CMD_MODE (1 << 21)
-#define PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE_AXI (0 << 21)
-#define PL354_SMC_DIRECT_CMD_ADDR_CS(interf,chip) (((interf) << 25) | ((chip) << 23))
+#define PL350_SMC_DIRECT_CMD_ADDR(addr) ((addr) & 0xFFFFF)
+#define PL350_SMC_DIRECT_CMD_ADDR_SET_CRE (1 << 20)
+#define PL350_SMC_DIRECT_CMD_ADDR_CMD_MODE_UPDATE (3 << 21)
+#define PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE (2 << 21)
+#define PL350_SMC_DIRECT_CMD_ADDR_CMD_MODE (1 << 21)
+#define PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE_AXI (0 << 21)
+#define PL350_SMC_DIRECT_CMD_ADDR_CS_INTERF(interf,chip) (((interf) << 25) | ((chip) << 23))
+#define PL350_SMC_DIRECT_CMD_ADDR_CS(ChipSelect) (((ChipSelect) & 0x7) << 23)
-#define PL354_SMC_SET_OPMODE_MEM_WIDTH_8 (0 << 0)
-#define PL354_SMC_SET_OPMODE_MEM_WIDTH_16 (1 << 0)
-#define PL354_SMC_SET_OPMODE_MEM_WIDTH_32 (2 << 0)
-#define PL354_SMC_SET_OPMODE_SET_RD_SYNC (1 << 2)
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_1 (0 << 3)
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_4 (1 << 3)
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_8 (2 << 3)
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_16 (3 << 3)
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_32 (4 << 3)
-#define PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT (5 << 3)
-#define PL354_SMC_SET_OPMODE_SET_WR_SYNC (1 << 6)
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_1 (0 << 7)
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_4 (1 << 7)
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_8 (2 << 7)
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_16 (3 << 7)
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_32 (4 << 7)
-#define PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT (5 << 7)
-#define PL354_SMC_SET_OPMODE_SET_BAA (1 << 10)
-#define PL354_SMC_SET_OPMODE_SET_ADV (1 << 11)
-#define PL354_SMC_SET_OPMODE_SET_BLS (1 << 12)
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_ANY (0 << 13)
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_32 (1 << 13)
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_64 (2 << 13)
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_128 (3 << 13)
-#define PL354_SMC_SET_OPMODE_SET_BURST_ALIGN_256 (4 << 13)
+#define PL350_SMC_SET_OPMODE_MEM_WIDTH_8 (0 << 0)
+#define PL350_SMC_SET_OPMODE_MEM_WIDTH_16 (1 << 0)
+#define PL350_SMC_SET_OPMODE_MEM_WIDTH_32 (2 << 0)
+#define PL350_SMC_SET_OPMODE_SET_RD_SYNC (1 << 2)
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_1 (0 << 3)
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_4 (1 << 3)
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_8 (2 << 3)
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_16 (3 << 3)
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_32 (4 << 3)
+#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT (5 << 3)
+#define PL350_SMC_SET_OPMODE_SET_WR_SYNC (1 << 6)
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_1 (0 << 7)
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_4 (1 << 7)
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_8 (2 << 7)
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_16 (3 << 7)
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_32 (4 << 7)
+#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT (5 << 7)
+#define PL350_SMC_SET_OPMODE_SET_BAA (1 << 10)
+#define PL350_SMC_SET_OPMODE_SET_ADV (1 << 11)
+#define PL350_SMC_SET_OPMODE_SET_BLS (1 << 12)
+#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_ANY (0 << 13)
+#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_32 (1 << 13)
+#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_64 (2 << 13)
+#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_128 (3 << 13)
+#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_256 (4 << 13)
+#define PL350_SMC_SET_CYCLE_NAND_T_RC(t) (((t) & 0xF) << 0)
+#define PL350_SMC_SET_CYCLE_NAND_T_WC(t) (((t) & 0xF) << 4)
+#define PL350_SMC_SET_CYCLE_NAND_T_REA(t) (((t) & 0x7) << 8)
+#define PL350_SMC_SET_CYCLE_NAND_T_WP(t) (((t) & 0x7) << 11)
+#define PL350_SMC_SET_CYCLE_NAND_T_CLR(t) (((t) & 0x7) << 14)
+#define PL350_SMC_SET_CYCLE_NAND_T_AR(t) (((t) & 0x7) << 17)
+#define PL350_SMC_SET_CYCLE_NAND_T_RR(t) (((t) & 0x7) << 20)
+
+#define PL350_SMC_SET_CYCLE_SRAM_T_RC(t) (((t) & 0xF) << 0)
+#define PL350_SMC_SET_CYCLE_SRAM_T_WC(t) (((t) & 0xF) << 4)
+#define PL350_SMC_SET_CYCLE_SRAM_T_CEOE(t) (((t) & 0x7) << 8)
+#define PL350_SMC_SET_CYCLE_SRAM_T_WP(t) (((t) & 0x7) << 11)
+#define PL350_SMC_SET_CYCLE_SRAM_T_PC(t) (((t) & 0x7) << 14)
+#define PL350_SMC_SET_CYCLE_SRAM_T_TR(t) (((t) & 0x7) << 17)
+#define PL350_SMC_SET_CYCLE_SRAM_WE_TIME (1 << 20)
#endif
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