ArmPlatformPkg: Code cleaning

- Fix coding style to follow EDK2 coding convention
- Remove deprecated function
- Remove unused PCDs



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11808 6f19259b-4bc3-4df7-8a09-765794883524

1 files changed, 47 insertions, 42 deletions

diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
index 2e6477d550..39de31a42a 100644
--- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
@@ -12,13 +12,14 @@
 *

 **/

 

-#include <PiPei.h>

 #include <Library/DebugLib.h>

 #include <Library/PcdLib.h>

 #include <Library/ArmMPCoreMailBoxLib.h>

 #include <Chipset/ArmV7.h>

 #include <Drivers/PL390Gic.h>

 

+#include "PrePeiCore.h"

+

 extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;

 

 /*

@@ -32,60 +33,64 @@ extern EFI_PEI_PPI_DESCRIPTOR *gSecPpiTable;
  */

 VOID

 EFIAPI

-secondary_main(IN UINTN CoreId)

+SecondaryMain (

+  IN UINTN CoreId

+  )

 {

-	//Function pointer to Secondary Core entry point

-	VOID (*secondary_start)(VOID);

-	UINTN secondary_entry_addr=0;

+  // Function pointer to Secondary Core entry point

+  VOID (*secondary_start)(VOID);

+  UINTN secondary_entry_addr=0;

 

-	//Clear Secondary cores MailBox

-	ArmClearMPCoreMailbox();

+  // Clear Secondary cores MailBox

+  ArmClearMPCoreMailbox();

 

-	while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {

-		ArmCallWFI();

-	  //Acknowledge the interrupt and send End of Interrupt signal.

-		PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);

-	}

+  while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {

+    ArmCallWFI();

+    // Acknowledge the interrupt and send End of Interrupt signal.

+    PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);

+  }

 

-	secondary_start = (VOID (*)())secondary_entry_addr;

+  secondary_start = (VOID (*)())secondary_entry_addr;

 

-	//Jump to secondary core entry point.

-	secondary_start();

+  // Jump to secondary core entry point.

+  secondary_start();

 

-	//the secondaries shouldn't reach here

-	ASSERT(FALSE);

+  // The secondaries shouldn't reach here

+  ASSERT(FALSE);

 }

 

-VOID primary_main (

+VOID

+EFIAPI

+PrimaryMain (

   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint

   )

 {

-	EFI_SEC_PEI_HAND_OFF        SecCoreData;

+  EFI_SEC_PEI_HAND_OFF        SecCoreData;

 

-	//Enable the GIC Distributor

-	PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));

+  //Enable the GIC Distributor

+  PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));

 

-	// If ArmVe has not been built as Standalone then we need to wake up the secondary cores

-	if (FeaturePcdGet(PcdStandalone) == FALSE) {

-		// Sending SGI to all the Secondary CPU interfaces

-		PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);

-	}

+  // If ArmVe has not been built as Standalone then we need to wake up the secondary cores

+  if (FeaturePcdGet(PcdStandalone) == FALSE) {

+    // Sending SGI to all the Secondary CPU interfaces

+    PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);

+  }

 

-	//

-	// Bind this information into the SEC hand-off state

-	// Note: this must be in sync with the stuff in the asm file

-	// Note also:  HOBs (pei temp ram) MUST be above stack

-	//

-	SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);

-    SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);

-    SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);

-	SecCoreData.TemporaryRamBase       = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)

-	SecCoreData.TemporaryRamSize       = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);

-	SecCoreData.PeiTemporaryRamBase    = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));

-	SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize / 2;

-	SecCoreData.StackBase              = SecCoreData.TemporaryRamBase;

-	SecCoreData.StackSize              = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;

+  //

+  // Bind this information into the SEC hand-off state

+  // Note: this must be in sync with the stuff in the asm file

+  // Note also:  HOBs (pei temp ram) MUST be above stack

+  //

+  SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);

+  SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdNormalFvBaseAddress);

+  SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdNormalFvSize);

+  SecCoreData.TemporaryRamBase       = (VOID *)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackBase); // We consider we run on the primary core (and so we use the first stack)

+  SecCoreData.TemporaryRamSize       = (UINTN)(UINTN)PcdGet32 (PcdCPUCoresNonSecStackSize);

+  SecCoreData.PeiTemporaryRamBase    = (VOID *)((UINTN)(SecCoreData.TemporaryRamBase) + (SecCoreData.TemporaryRamSize / 2));

+  SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize / 2;

+  SecCoreData.StackBase              = SecCoreData.TemporaryRamBase;

+  SecCoreData.StackSize              = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;

 

-	// jump to pei core entry point

-	(PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);

+  // Jump to PEI core entry point

+  (PeiCoreEntryPoint)(&SecCoreData, (VOID *)&gSecPpiTable);

 }