ArmPlatformPkg: Apply uncrustify changes

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the ArmPlatformPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Andrew Fish <afish@apple.com>

6 files changed, 132 insertions, 122 deletions

diff --git a/ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c b/ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c
index 5d3d1911a0..2dc77f4b87 100644
--- a/ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c
+++ b/ArmPlatformPkg/PrePeiCore/AArch64/ArchPrePeiCore.c
@@ -14,33 +14,33 @@
 

 VOID

 PeiCommonExceptionEntry (

-  IN UINT32 Entry,

-  IN UINTN LR

+  IN UINT32  Entry,

+  IN UINTN   LR

   )

 {

-  CHAR8           Buffer[100];

-  UINTN           CharCount;

+  CHAR8  Buffer[100];

+  UINTN  CharCount;

 

   switch (Entry) {

-  case EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS:

-    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Synchronous Exception at 0x%X\n\r", LR);

-    break;

-  case EXCEPT_AARCH64_IRQ:

-    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r", LR);

-    break;

-  case EXCEPT_AARCH64_FIQ:

-    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r", LR);

-    break;

-  case EXCEPT_AARCH64_SERROR:

-    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SError/Abort Exception at 0x%X\n\r", LR);

-    break;

-  default:

-    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r", LR);

-    break;

+    case EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS:

+      CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Synchronous Exception at 0x%X\n\r", LR);

+      break;

+    case EXCEPT_AARCH64_IRQ:

+      CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "IRQ Exception at 0x%X\n\r", LR);

+      break;

+    case EXCEPT_AARCH64_FIQ:

+      CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "FIQ Exception at 0x%X\n\r", LR);

+      break;

+    case EXCEPT_AARCH64_SERROR:

+      CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "SError/Abort Exception at 0x%X\n\r", LR);

+      break;

+    default:

+      CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Unknown Exception at 0x%X\n\r", LR);

+      break;

   }

 

-  SerialPortWrite ((UINT8 *) Buffer, CharCount);

+  SerialPortWrite ((UINT8 *)Buffer, CharCount);

 

-  while(1);

+  while (1) {

+  }

 }

-

diff --git a/ArmPlatformPkg/PrePeiCore/Arm/ArchPrePeiCore.c b/ArmPlatformPkg/PrePeiCore/Arm/ArchPrePeiCore.c
index 433f2de961..debf328803 100644
--- a/ArmPlatformPkg/PrePeiCore/Arm/ArchPrePeiCore.c
+++ b/ArmPlatformPkg/PrePeiCore/Arm/ArchPrePeiCore.c
@@ -14,43 +14,44 @@
 

 VOID

 PeiCommonExceptionEntry (

-  IN UINT32 Entry,

-  IN UINTN LR

+  IN UINT32  Entry,

+  IN UINTN   LR

   )

 {

-  CHAR8           Buffer[100];

-  UINTN           CharCount;

+  CHAR8  Buffer[100];

+  UINTN  CharCount;

 

   switch (Entry) {

-  case 0:

-    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR);

-    break;

-  case 1:

-    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR);

-    break;

-  case 2:

-    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR);

-    break;

-  case 3:

-    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR);

-    break;

-  case 4:

-    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR);

-    break;

-  case 5:

-    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR);

-    break;

-  case 6:

-    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR);

-    break;

-  case 7:

-    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR);

-    break;

-  default:

-    CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR);

-    break;

+    case 0:

+      CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Reset Exception at 0x%X\n\r", LR);

+      break;

+    case 1:

+      CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Undefined Exception at 0x%X\n\r", LR);

+      break;

+    case 2:

+      CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "SWI Exception at 0x%X\n\r", LR);

+      break;

+    case 3:

+      CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "PrefetchAbort Exception at 0x%X\n\r", LR);

+      break;

+    case 4:

+      CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "DataAbort Exception at 0x%X\n\r", LR);

+      break;

+    case 5:

+      CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Reserved Exception at 0x%X\n\r", LR);

+      break;

+    case 6:

+      CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "IRQ Exception at 0x%X\n\r", LR);

+      break;

+    case 7:

+      CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "FIQ Exception at 0x%X\n\r", LR);

+      break;

+    default:

+      CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "Unknown Exception at 0x%X\n\r", LR);

+      break;

   }

-  SerialPortWrite ((UINT8 *) Buffer, CharCount);

-  while(1);

-}

 

+  SerialPortWrite ((UINT8 *)Buffer, CharCount);

+  while (1) {

+  }

+}

diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
index 859f1adf20..0b8e5dfb3f 100644
--- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
@@ -24,7 +24,7 @@
 VOID

 EFIAPI

 SecondaryMain (

-  IN UINTN MpId

+  IN UINTN  MpId

   )

 {

   EFI_STATUS              Status;

@@ -37,18 +37,21 @@ SecondaryMain (
   ARM_CORE_INFO           *ArmCoreInfoTable;

   UINT32                  ClusterId;

   UINT32                  CoreId;

-  VOID                    (*SecondaryStart)(VOID);

-  UINTN                   SecondaryEntryAddr;

-  UINTN                   AcknowledgeInterrupt;

-  UINTN                   InterruptId;

 

-  ClusterId = GET_CLUSTER_ID(MpId);

-  CoreId    = GET_CORE_ID(MpId);

+  VOID  (*SecondaryStart)(

+    VOID

+    );

+  UINTN  SecondaryEntryAddr;

+  UINTN  AcknowledgeInterrupt;

+  UINTN  InterruptId;

+

+  ClusterId = GET_CLUSTER_ID (MpId);

+  CoreId    = GET_CORE_ID (MpId);

 

   // Get the gArmMpCoreInfoPpiGuid

   PpiListSize = 0;

   ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);

-  PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);

+  PpiListCount = PpiListSize / sizeof (EFI_PEI_PPI_DESCRIPTOR);

   for (Index = 0; Index < PpiListCount; Index++, PpiList++) {

     if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {

       break;

@@ -59,8 +62,8 @@ SecondaryMain (
   ASSERT (Index != PpiListCount);

 

   ArmMpCoreInfoPpi = PpiList->Ppi;

-  ArmCoreCount = 0;

-  Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);

+  ArmCoreCount     = 0;

+  Status           = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);

   ASSERT_EFI_ERROR (Status);

 

   // Find the core in the ArmCoreTable

@@ -92,11 +95,11 @@ SecondaryMain (
   } while (SecondaryEntryAddr == 0);

 

   // Jump to secondary core entry point.

-  SecondaryStart = (VOID (*)())SecondaryEntryAddr;

-  SecondaryStart();

+  SecondaryStart = (VOID (*)()) SecondaryEntryAddr;

+  SecondaryStart ();

 

   // The secondaries shouldn't reach here

-  ASSERT(FALSE);

+  ASSERT (FALSE);

 }

 

 VOID

@@ -105,26 +108,26 @@ PrimaryMain (
   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint

   )

 {

-  EFI_SEC_PEI_HAND_OFF        SecCoreData;

-  UINTN                       PpiListSize;

-  EFI_PEI_PPI_DESCRIPTOR      *PpiList;

-  UINTN                       TemporaryRamBase;

-  UINTN                       TemporaryRamSize;

+  EFI_SEC_PEI_HAND_OFF    SecCoreData;

+  UINTN                   PpiListSize;

+  EFI_PEI_PPI_DESCRIPTOR  *PpiList;

+  UINTN                   TemporaryRamBase;

+  UINTN                   TemporaryRamSize;

 

   CreatePpiList (&PpiListSize, &PpiList);

 

   // Enable the GIC Distributor

-  ArmGicEnableDistributor (PcdGet64(PcdGicDistributorBase));

+  ArmGicEnableDistributor (PcdGet64 (PcdGicDistributorBase));

 

   // If ArmVe has not been built as Standalone then we need to wake up the secondary cores

   if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {

     // Sending SGI to all the Secondary CPU interfaces

-    ArmGicSendSgiTo (PcdGet64(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));

+    ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));

   }

 

   // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at

   // the base of the primary core stack

-  PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT);

+  PpiListSize      = ALIGN_VALUE (PpiListSize, CPU_STACK_ALIGNMENT);

   TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;

   TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;

 

@@ -133,7 +136,7 @@ PrimaryMain (
   // Note: this must be in sync with the stuff in the asm file

   // Note also:  HOBs (pei temp ram) MUST be above stack

   //

-  SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);

+  SecCoreData.DataSize               = sizeof (EFI_SEC_PEI_HAND_OFF);

   SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);

   SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);

   SecCoreData.TemporaryRamBase       = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)

diff --git a/ArmPlatformPkg/PrePeiCore/MainUniCore.c b/ArmPlatformPkg/PrePeiCore/MainUniCore.c
index 220f9b5680..1c2580eb92 100644
--- a/ArmPlatformPkg/PrePeiCore/MainUniCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainUniCore.c
@@ -11,10 +11,10 @@
 VOID

 EFIAPI

 SecondaryMain (

-  IN UINTN MpId

+  IN UINTN  MpId

   )

 {

-  ASSERT(FALSE);

+  ASSERT (FALSE);

 }

 

 VOID

@@ -23,17 +23,17 @@ PrimaryMain (
   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint

   )

 {

-  EFI_SEC_PEI_HAND_OFF        SecCoreData;

-  UINTN                       PpiListSize;

-  EFI_PEI_PPI_DESCRIPTOR      *PpiList;

-  UINTN                       TemporaryRamBase;

-  UINTN                       TemporaryRamSize;

+  EFI_SEC_PEI_HAND_OFF    SecCoreData;

+  UINTN                   PpiListSize;

+  EFI_PEI_PPI_DESCRIPTOR  *PpiList;

+  UINTN                   TemporaryRamBase;

+  UINTN                   TemporaryRamSize;

 

   CreatePpiList (&PpiListSize, &PpiList);

 

   // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at

   // the base of the primary core stack

-  PpiListSize = ALIGN_VALUE(PpiListSize, CPU_STACK_ALIGNMENT);

+  PpiListSize      = ALIGN_VALUE (PpiListSize, CPU_STACK_ALIGNMENT);

   TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;

   TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;

 

@@ -42,7 +42,7 @@ PrimaryMain (
   // Note: this must be in sync with the stuff in the asm file

   // Note also:  HOBs (pei temp ram) MUST be above stack

   //

-  SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);

+  SecCoreData.DataSize               = sizeof (EFI_SEC_PEI_HAND_OFF);

   SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);

   SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);

   SecCoreData.TemporaryRamBase       = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)

diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
index 69dbb77dee..6dd9bcdea2 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
@@ -14,13 +14,13 @@
 

 #include "PrePeiCore.h"

 

-CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI   mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };

+CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI  mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };

 

-CONST EFI_PEI_PPI_DESCRIPTOR      gCommonPpiTable[] = {

+CONST EFI_PEI_PPI_DESCRIPTOR  gCommonPpiTable[] = {

   {

     EFI_PEI_PPI_DESCRIPTOR_PPI,

     &gEfiTemporaryRamSupportPpiGuid,

-    (VOID *) &mTemporaryRamSupportPpi

+    (VOID *)&mTemporaryRamSupportPpi

   }

 };

 

@@ -30,10 +30,10 @@ CreatePpiList (
   OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList

   )

 {

-  EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList;

+  EFI_PEI_PPI_DESCRIPTOR  *PlatformPpiList;

   UINTN                   PlatformPpiListSize;

   UINTN                   ListBase;

-  EFI_PEI_PPI_DESCRIPTOR *LastPpi;

+  EFI_PEI_PPI_DESCRIPTOR  *LastPpi;

 

   // Get the Platform PPIs

   PlatformPpiListSize = 0;

@@ -41,15 +41,15 @@ CreatePpiList (
 

   // Copy the Common and Platform PPis in Temporary Memory

   ListBase = PcdGet64 (PcdCPUCoresStackBase);

-  CopyMem ((VOID*)ListBase, gCommonPpiTable, sizeof(gCommonPpiTable));

-  CopyMem ((VOID*)(ListBase + sizeof(gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);

+  CopyMem ((VOID *)ListBase, gCommonPpiTable, sizeof (gCommonPpiTable));

+  CopyMem ((VOID *)(ListBase + sizeof (gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);

 

   // Set the Terminate flag on the last PPI entry

-  LastPpi = (EFI_PEI_PPI_DESCRIPTOR*)ListBase + ((sizeof(gCommonPpiTable) + PlatformPpiListSize) / sizeof(EFI_PEI_PPI_DESCRIPTOR)) - 1;

+  LastPpi         = (EFI_PEI_PPI_DESCRIPTOR *)ListBase + ((sizeof (gCommonPpiTable) + PlatformPpiListSize) / sizeof (EFI_PEI_PPI_DESCRIPTOR)) - 1;

   LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;

 

-  *PpiList     = (EFI_PEI_PPI_DESCRIPTOR*)ListBase;

-  *PpiListSize = sizeof(gCommonPpiTable) + PlatformPpiListSize;

+  *PpiList     = (EFI_PEI_PPI_DESCRIPTOR *)ListBase;

+  *PpiListSize = sizeof (gCommonPpiTable) + PlatformPpiListSize;

 }

 

 VOID

@@ -65,8 +65,10 @@ CEntryPoint (
   // Enable Instruction Caches on all cores.

   ArmEnableInstructionCache ();

 

-  InvalidateDataCacheRange ((VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),

-                            PcdGet32 (PcdCPUCorePrimaryStackSize));

+  InvalidateDataCacheRange (

+    (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),

+    PcdGet32 (PcdCPUCorePrimaryStackSize)

+    );

 

   //

   // Note: Doesn't have to Enable CPU interface in non-secure world,

@@ -84,7 +86,7 @@ CEntryPoint (
     ArmEnableVFP ();

   }

 

-  //Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.

+  // Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.

 

   // If not primary Jump to Secondary Main

   if (ArmPlatformIsPrimaryCore (MpId)) {

@@ -108,25 +110,25 @@ CEntryPoint (
 EFI_STATUS

 EFIAPI

 PrePeiCoreTemporaryRamSupport (

-  IN CONST EFI_PEI_SERVICES   **PeiServices,

-  IN EFI_PHYSICAL_ADDRESS     TemporaryMemoryBase,

-  IN EFI_PHYSICAL_ADDRESS     PermanentMemoryBase,

-  IN UINTN                    CopySize

+  IN CONST EFI_PEI_SERVICES  **PeiServices,

+  IN EFI_PHYSICAL_ADDRESS    TemporaryMemoryBase,

+  IN EFI_PHYSICAL_ADDRESS    PermanentMemoryBase,

+  IN UINTN                   CopySize

   )

 {

-  VOID                             *OldHeap;

-  VOID                             *NewHeap;

-  VOID                             *OldStack;

-  VOID                             *NewStack;

-  UINTN                            HeapSize;

+  VOID   *OldHeap;

+  VOID   *NewHeap;

+  VOID   *OldStack;

+  VOID   *NewStack;

+  UINTN  HeapSize;

 

   HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT);

 

-  OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;

-  NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize - HeapSize));

+  OldHeap = (VOID *)(UINTN)TemporaryMemoryBase;

+  NewHeap = (VOID *)((UINTN)PermanentMemoryBase + (CopySize - HeapSize));

 

-  OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize);

-  NewStack = (VOID*)(UINTN)PermanentMemoryBase;

+  OldStack = (VOID *)((UINTN)TemporaryMemoryBase + HeapSize);

+  NewStack = (VOID *)(UINTN)PermanentMemoryBase;

 

   //

   // Migrate the temporary memory stack to permanent memory stack.

diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.h b/ArmPlatformPkg/PrePeiCore/PrePeiCore.h
index 7b155a8a61..0345dd7bdd 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.h
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.h
@@ -6,6 +6,7 @@
   SPDX-License-Identifier: BSD-2-Clause-Patent

 

 **/

+

 #ifndef __PREPEICORE_H_

 #define __PREPEICORE_H_

 

@@ -28,19 +29,22 @@ CreatePpiList (
 EFI_STATUS

 EFIAPI

 PrePeiCoreTemporaryRamSupport (

-  IN CONST EFI_PEI_SERVICES   **PeiServices,

-  IN EFI_PHYSICAL_ADDRESS     TemporaryMemoryBase,

-  IN EFI_PHYSICAL_ADDRESS     PermanentMemoryBase,

-  IN UINTN                    CopySize

+  IN CONST EFI_PEI_SERVICES  **PeiServices,

+  IN EFI_PHYSICAL_ADDRESS    TemporaryMemoryBase,

+  IN EFI_PHYSICAL_ADDRESS    PermanentMemoryBase,

+  IN UINTN                   CopySize

   );

 

 VOID

 SecSwitchStack (

-  INTN    StackDelta

+  INTN  StackDelta

   );

 

 // Vector Table for Pei Phase

-VOID  PeiVectorTable (VOID);

+VOID

+PeiVectorTable (

+  VOID

+  );

 

 VOID

 EFIAPI

@@ -60,13 +64,13 @@ PrimaryMain (
 VOID

 EFIAPI

 SecondaryMain (

-  IN UINTN MpId

+  IN UINTN  MpId

   );

 

 VOID

 PeiCommonExceptionEntry (

-  IN UINT32 Entry,

-  IN UINTN LR

+  IN UINT32  Entry,

+  IN UINTN   LR

   );

 

 #endif