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| author | Olivier Martin <olivier.martin@arm.com> | 2014-07-15 09:24:25 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-07-15 09:24:25 +0000 |
| commit | 6d0ca2577c3788ee1087177df439246fe8f2b4fd (patch) | |
| tree | f69fff3250c6dd18b8d8ef558252e35d29a5227b /ArmPlatformPkg/PrePeiCore | |
| parent | 9232ee533884b4b516b3979ce355e367a6254749 (diff) | |
| download | edk2-6d0ca2577c3788ee1087177df439246fe8f2b4fd.tar.gz edk2-6d0ca2577c3788ee1087177df439246fe8f2b4fd.tar.bz2 edk2-6d0ca2577c3788ee1087177df439246fe8f2b4fd.zip | |
ARM Packages: Force the SEC modules to be 2K aligned for AArch64
The AArch64 Vector Table must be aligned on a 2K boundary.
The FDF specification does not support 2K alignment but support 4K.
A clear comment has been added to help integrator to understand why the
assertion fails when porting to a new AArch64 platform.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15659 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPlatformPkg/PrePeiCore')
| -rw-r--r-- | ArmPlatformPkg/PrePeiCore/PrePeiCore.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c index 1abefaefd2..f33f376cf1 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c @@ -1,7 +1,7 @@ /** @file
* Main file supporting the transition to PEI Core in Normal World for Versatile Express
*
-* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
@@ -86,8 +86,9 @@ CEntryPoint ( //
// Write VBAR - The Exception Vector table must be aligned to its requirement
- //TODO: Fix baseTools to ensure the Exception Vector Table is correctly aligned in AArch64
- //ASSERT(((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
+ // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure
+ // 'Align=4K' is defined into your FDF for this module.
+ ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
ArmWriteVBar ((UINTN)PeiVectorTable);
//Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.
|