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| author | Olivier Martin <olivier.martin@arm.com> | 2013-08-21 12:05:44 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2013-08-21 12:05:44 +0000 |
| commit | cc9355448601a16089b633ebb0a9d01086e5c91f (patch) | |
| tree | 62df6445b78b6ebc58d46f7e0529c39946184a5f /ArmPlatformPkg/Sec | |
| parent | a639401d2fb4fccc7830065e74c8782700035adf (diff) | |
| download | edk2-cc9355448601a16089b633ebb0a9d01086e5c91f.tar.gz edk2-cc9355448601a16089b633ebb0a9d01086e5c91f.tar.bz2 edk2-cc9355448601a16089b633ebb0a9d01086e5c91f.zip | |
ArmPlatformPkg/Sec: Remove SCR and CPTR initialization from SetupExceptionLevel3
This is already taken care by Sec when PcdTrustzoneSupport = TRUE.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14580 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPlatformPkg/Sec')
| -rw-r--r-- | ArmPlatformPkg/Sec/AArch64/Helper.S | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/ArmPlatformPkg/Sec/AArch64/Helper.S b/ArmPlatformPkg/Sec/AArch64/Helper.S index ff46255763..3b833bad7c 100644 --- a/ArmPlatformPkg/Sec/AArch64/Helper.S +++ b/ArmPlatformPkg/Sec/AArch64/Helper.S @@ -26,20 +26,6 @@ ASM_GLOBAL ASM_PFX(copy_cpsr_into_spsr) ASM_GLOBAL ASM_PFX(set_non_secure_mode)
ASM_PFX(SetupExceptionLevel3):
- mrs x0, scr_el3 // Read EL3 Secure Configuration Register
- orr x0, x0, #1 // EL0 an EL1 cannot access secure memory
-
- // Send all interrupts to their respective Exception levels for EL3
- bic x0, x0, #(1 << 1) // IRQ
- bic x0, x0, #(1 << 2) // FIQ
- bic x0, x0, #(1 << 3) // Serror and Abort
- orr x0, x0, #(1 << 8) // Enable HVC
- orr x0, x0, #(1 << 10) // Make next level down 64Bit. This is EL2 in the case of the Model.
- // We need a nice way to detect this.
- msr scr_el3, x0 // Write back our settings
-
- msr cptr_el3, xzr // Disable copro traps to EL3
-
// Check for the primary CPU to avoid a race on the distributor registers.
mrs x0, mpidr_el1
tst x0, #15
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