ArmPkg ArmPlatformPkg ArmVirtPkg: ARM GICv2/v3 Base Address width fix-up

According to the ACPI 6.0/6.1 spec, the physical base address of GICC,
GICD, GICR and GIC ITS is 64-bit. So change the type of the various GIC
base address PCDs to 64-bit, and fix up all users.

Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Dennis Chen <dennis.chen@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

4 files changed, 15 insertions, 15 deletions

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/RTSMSec.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/RTSMSec.c
index 9023715ab0..754a36d562 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/RTSMSec.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/RTSMSec.c
@@ -73,7 +73,7 @@ ArmPlatformSecInitialize (
   MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);

 

   // Read the GIC Identification Register

-  Identification = ArmGicGetInterfaceIdentification (PcdGet32 (PcdGicInterruptInterfaceBase));

+  Identification = ArmGicGetInterfaceIdentification (PcdGet64 (PcdGicInterruptInterfaceBase));

 

   // Check if we are GICv3

   if (ARM_GIC_ICCIIDR_GET_ARCH_VERSION(Identification) >= 0x3) {

diff --git a/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c b/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c
index a452e38751..e617bdaa9c 100644
--- a/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c
+++ b/ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c
@@ -40,11 +40,11 @@ NonSecureWaitForFirmware (
   ArmCallWFI ();

 

   // Acknowledge the interrupt and send End of Interrupt signal.

-  AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), &InterruptId);

+  AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), &InterruptId);

   // Check if it is a valid interrupt ID

-  if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {

+  if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet64 (PcdGicDistributorBase))) {

     // Got a valid SGI number hence signal End of Interrupt

-    ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);

+    ArmGicEndOfInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);

   }

 

   // Jump to secondary core entry point.

@@ -105,7 +105,7 @@ ArmPlatformSecExtraAction (
 

     if (ArmPlatformIsPrimaryCore (MpId)) {

       // Signal the secondary cores they can jump to PEI phase

-      ArmGicSendSgiTo (PcdGet32 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));

+      ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));

 

       // To enter into Non Secure state, we need to make a return from exception

       *JumpAddress = PcdGet64 (PcdFvBaseAddress);

diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
index fa544c79f9..dc47adbaff 100644
--- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
@@ -89,11 +89,11 @@ SecondaryMain (
     SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);

 

     // Acknowledge the interrupt and send End of Interrupt signal.

-    AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), &InterruptId);

+    AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), &InterruptId);

     // Check if it is a valid interrupt ID

-    if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {

+    if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet64 (PcdGicDistributorBase))) {

       // Got a valid SGI number hence signal End of Interrupt

-      ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);

+      ArmGicEndOfInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);

     }

   } while (SecondaryEntryAddr == 0);

 

@@ -120,12 +120,12 @@ PrimaryMain (
   CreatePpiList (&PpiListSize, &PpiList);

 

   // Enable the GIC Distributor

-  ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));

+  ArmGicEnableDistributor (PcdGet64(PcdGicDistributorBase));

 

   // If ArmVe has not been built as Standalone then we need to wake up the secondary cores

   if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {

     // Sending SGI to all the Secondary CPU interfaces

-    ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));

+    ArmGicSendSgiTo (PcdGet64(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));

   }

 

   // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at

diff --git a/ArmPlatformPkg/PrePi/MainMPCore.c b/ArmPlatformPkg/PrePi/MainMPCore.c
index 603f4bb8be..27422d1f21 100644
--- a/ArmPlatformPkg/PrePi/MainMPCore.c
+++ b/ArmPlatformPkg/PrePi/MainMPCore.c
@@ -26,12 +26,12 @@ PrimaryMain (
   )

 {

   // Enable the GIC Distributor

-  ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));

+  ArmGicEnableDistributor(PcdGet64(PcdGicDistributorBase));

 

   // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader to resume their initialization

   if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {

     // Sending SGI to all the Secondary CPU interfaces

-    ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));

+    ArmGicSendSgiTo (PcdGet64(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));

   }

 

   PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp);

@@ -88,11 +88,11 @@ SecondaryMain (
     SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);

 

     // Acknowledge the interrupt and send End of Interrupt signal.

-    AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), &InterruptId);

+    AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), &InterruptId);

     // Check if it is a valid interrupt ID

-    if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet32 (PcdGicDistributorBase))) {

+    if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet64 (PcdGicDistributorBase))) {

       // Got a valid SGI number hence signal End of Interrupt

-      ArmGicEndOfInterrupt (PcdGet32 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);

+      ArmGicEndOfInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);

     }

   } while (SecondaryEntryAddr == 0);