ArmPlatformPkg/PrePeiCore: Drop MPCore variant

The PrePeiCore SEC driver can be built in unicore and MPcore versions
from [mostly] the same source. The latter is obsolete, so remove it and
simplify the remaining code accordingly.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>

7 files changed, 11 insertions, 272 deletions

diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec
index 7b5d7e6cb5..be384524bd 100644
--- a/ArmPlatformPkg/ArmPlatformPkg.dec
+++ b/ArmPlatformPkg/ArmPlatformPkg.dec
@@ -50,8 +50,6 @@
   gArmPlatformTokenSpaceGuid   = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }

 

 [PcdsFeatureFlag.common]

-  gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004

-

   # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,

   # we assume the OS will handle the FrameBuffer from the UEFI GOP information.

   gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D

diff --git a/ArmPlatformPkg/ArmPlatformPkg.dsc b/ArmPlatformPkg/ArmPlatformPkg.dsc
index 72d4eb4b2c..bc4160d931 100644
--- a/ArmPlatformPkg/ArmPlatformPkg.dsc
+++ b/ArmPlatformPkg/ArmPlatformPkg.dsc
@@ -120,7 +120,6 @@
   ArmPlatformPkg/PlatformPei/PlatformPeim.inf

   ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf

 

-  ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf

   ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf

 

   ArmPlatformPkg/PrePi/PeiUniCore.inf

diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
deleted file mode 100644
index b5d0d3a644..0000000000
--- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/** @file

-

-  Copyright (c) 2011-2014, ARM Limited. All rights reserved.

-

-  SPDX-License-Identifier: BSD-2-Clause-Patent

-

-**/

-

-#include <Library/ArmGicLib.h>

-

-#include <Ppi/ArmMpCoreInfo.h>

-

-#include "PrePeiCore.h"

-

-/*

- * This is the main function for secondary cores. They loop around until a non Null value is written to

- * SYS_FLAGS register.The SYS_FLAGS register is platform specific.

- * Note:The secondary cores, while executing secondary_main, assumes that:

- *      : SGI 0 is configured as Non-secure interrupt

- *      : Priority Mask is configured to allow SGI 0

- *      : Interrupt Distributor and CPU interfaces are enabled

- *

- */

-VOID

-EFIAPI

-SecondaryMain (

-  IN UINTN  MpId

-  )

-{

-  EFI_STATUS              Status;

-  UINTN                   PpiListSize;

-  UINTN                   PpiListCount;

-  EFI_PEI_PPI_DESCRIPTOR  *PpiList;

-  ARM_MP_CORE_INFO_PPI    *ArmMpCoreInfoPpi;

-  UINTN                   Index;

-  UINTN                   ArmCoreCount;

-  ARM_CORE_INFO           *ArmCoreInfoTable;

-  UINT32                  ClusterId;

-  UINT32                  CoreId;

-

-  VOID  (*SecondaryStart)(

-    VOID

-    );

-  UINTN  SecondaryEntryAddr;

-  UINTN  AcknowledgeInterrupt;

-  UINTN  InterruptId;

-

-  ClusterId = GET_CLUSTER_ID (MpId);

-  CoreId    = GET_CORE_ID (MpId);

-

-  // Get the gArmMpCoreInfoPpiGuid

-  PpiListSize = 0;

-  ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);

-  PpiListCount = PpiListSize / sizeof (EFI_PEI_PPI_DESCRIPTOR);

-  for (Index = 0; Index < PpiListCount; Index++, PpiList++) {

-    if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {

-      break;

-    }

-  }

-

-  // On MP Core Platform we must implement the ARM MP Core Info PPI

-  ASSERT (Index != PpiListCount);

-

-  ArmMpCoreInfoPpi = PpiList->Ppi;

-  ArmCoreCount     = 0;

-  Status           = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);

-  ASSERT_EFI_ERROR (Status);

-

-  // Find the core in the ArmCoreTable

-  for (Index = 0; Index < ArmCoreCount; Index++) {

-    if ((GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr) == ClusterId) &&

-        (GET_MPIDR_AFF0 (ArmCoreInfoTable[Index].Mpidr) == CoreId))

-    {

-      break;

-    }

-  }

-

-  // The ARM Core Info Table must define every core

-  ASSERT (Index != ArmCoreCount);

-

-  // Clear Secondary cores MailBox

-  MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);

-

-  do {

-    ArmCallWFI ();

-

-    // Read the Mailbox

-    SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);

-

-    // Acknowledge the interrupt and send End of Interrupt signal.

-    AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), &InterruptId);

-    // Check if it is a valid interrupt ID

-    if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet64 (PcdGicDistributorBase))) {

-      // Got a valid SGI number hence signal End of Interrupt

-      ArmGicEndOfInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);

-    }

-  } while (SecondaryEntryAddr == 0);

-

-  // Jump to secondary core entry point.

-  SecondaryStart = (VOID (*)()) SecondaryEntryAddr;

-  SecondaryStart ();

-

-  // The secondaries shouldn't reach here

-  ASSERT (FALSE);

-}

-

-VOID

-EFIAPI

-PrimaryMain (

-  IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint

-  )

-{

-  EFI_SEC_PEI_HAND_OFF    SecCoreData;

-  UINTN                   PpiListSize;

-  EFI_PEI_PPI_DESCRIPTOR  *PpiList;

-  UINTN                   TemporaryRamBase;

-  UINTN                   TemporaryRamSize;

-

-  CreatePpiList (&PpiListSize, &PpiList);

-

-  // Enable the GIC Distributor

-  ArmGicEnableDistributor (PcdGet64 (PcdGicDistributorBase));

-

-  // If ArmVe has not been built as Standalone then we need to wake up the secondary cores

-  if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {

-    // Sending SGI to all the Secondary CPU interfaces

-    ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));

-  }

-

-  // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at

-  // the base of the primary core stack

-  PpiListSize      = ALIGN_VALUE (PpiListSize, CPU_STACK_ALIGNMENT);

-  TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;

-  TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;

-

-  //

-  // Bind this information into the SEC hand-off state

-  // Note: this must be in sync with the stuff in the asm file

-  // Note also:  HOBs (pei temp ram) MUST be above stack

-  //

-  SecCoreData.DataSize               = sizeof (EFI_SEC_PEI_HAND_OFF);

-  SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);

-  SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);

-  SecCoreData.TemporaryRamBase       = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)

-  SecCoreData.TemporaryRamSize       = TemporaryRamSize;

-  SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;

-  SecCoreData.PeiTemporaryRamSize    = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);

-  SecCoreData.StackBase              = (VOID *)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);

-  SecCoreData.StackSize              = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;

-

-  // Jump to PEI core entry point

-  PeiCoreEntryPoint (&SecCoreData, PpiList);

-}

diff --git a/ArmPlatformPkg/PrePeiCore/MainUniCore.c b/ArmPlatformPkg/PrePeiCore/MainUniCore.c
index 1c2580eb92..3d3c6caaa3 100644
--- a/ArmPlatformPkg/PrePeiCore/MainUniCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainUniCore.c
@@ -10,15 +10,6 @@
 

 VOID

 EFIAPI

-SecondaryMain (

-  IN UINTN  MpId

-  )

-{

-  ASSERT (FALSE);

-}

-

-VOID

-EFIAPI

 PrimaryMain (

   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint

   )

diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
index 42a7ccc9c6..b4d40e7156 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
@@ -117,26 +117,21 @@ CEntryPoint (
 

   // Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.

 

-  // If not primary Jump to Secondary Main

-  if (ArmPlatformIsPrimaryCore (MpId)) {

-    // Invoke "ProcessLibraryConstructorList" to have all library constructors

-    // called.

-    ProcessLibraryConstructorList ();

+  // Invoke "ProcessLibraryConstructorList" to have all library constructors

+  // called.

+  ProcessLibraryConstructorList ();

 

-    PrintFirmwareVersion ();

+  PrintFirmwareVersion ();

 

-    // Initialize the Debug Agent for Source Level Debugging

-    InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);

-    SaveAndSetDebugTimerInterrupt (TRUE);

+  // Initialize the Debug Agent for Source Level Debugging

+  InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);

+  SaveAndSetDebugTimerInterrupt (TRUE);

 

-    // Initialize the platform specific controllers

-    ArmPlatformInitialize (MpId);

+  // Initialize the platform specific controllers

+  ArmPlatformInitialize (MpId);

 

-    // Goto primary Main.

-    PrimaryMain (PeiCoreEntryPoint);

-  } else {

-    SecondaryMain (MpId);

-  }

+  // Goto primary Main.

+  PrimaryMain (PeiCoreEntryPoint);

 

   // PEI Core should always load and never return

   ASSERT (FALSE);

diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.h b/ArmPlatformPkg/PrePeiCore/PrePeiCore.h
index fbf6207db8..966b0e7eee 100644
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.h
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.h
@@ -52,21 +52,6 @@ PrimaryMain (
   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint

   );

 

-/*

- * This is the main function for secondary cores. They loop around until a non Null value is written to

- * SYS_FLAGS register.The SYS_FLAGS register is platform specific.

- * Note:The secondary cores, while executing secondary_main, assumes that:

- *      : SGI 0 is configured as Non-secure interrupt

- *      : Priority Mask is configured to allow SGI 0

- *      : Interrupt Distributor and CPU interfaces are enabled

- *

- */

-VOID

-EFIAPI

-SecondaryMain (

-  IN UINTN  MpId

-  );

-

 VOID

 PeiCommonExceptionEntry (

   IN UINT32  Entry,

diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
deleted file mode 100644
index c5cad7e37f..0000000000
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+++ /dev/null
@@ -1,76 +0,0 @@
-#/** @file

-#  Pre PeiCore - Hand-off to PEI Core in Normal World

-#

-#  Copyright (c) 2011-2014, ARM Limited. All rights reserved.

-#

-#  SPDX-License-Identifier: BSD-2-Clause-Patent

-#

-#**/

-

-[Defines]

-  INF_VERSION                    = 1.30

-  BASE_NAME                      = ArmPlatformPrePeiCore

-  FILE_GUID                      = b78d02bb-d0b5-4389-bc7f-b39ee846c784

-  MODULE_TYPE                    = SEC

-  VERSION_STRING                 = 1.0

-

-[Sources.common]

-  MainMPCore.c

-  PrePeiCore.h

-  PrePeiCore.c

-

-[Sources.ARM]

-  Arm/ArchPrePeiCore.c

-  Arm/PrePeiCoreEntryPoint.S   | GCC

-  Arm/SwitchStack.S        | GCC

-  Arm/Exception.S          | GCC

-

-[Sources.AARCH64]

-  AArch64/ArchPrePeiCore.c

-  AArch64/PrePeiCoreEntryPoint.S

-  AArch64/SwitchStack.S

-  AArch64/Exception.S

-  AArch64/Helper.S

-

-[Packages]

-  MdePkg/MdePkg.dec

-  MdeModulePkg/MdeModulePkg.dec

-  ArmPkg/ArmPkg.dec

-  ArmPlatformPkg/ArmPlatformPkg.dec

-

-[LibraryClasses]

-  ArmLib

-  ArmPlatformLib

-  CacheMaintenanceLib

-  BaseLib

-  DebugLib

-  DebugAgentLib

-  IoLib

-  ArmGicLib

-  PrintLib

-  SerialPortLib

-

-[Ppis]

-  gEfiTemporaryRamSupportPpiGuid

-  gArmMpCoreInfoPpiGuid

-

-[Pcd]

-  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString

-

-[FeaturePcd]

-  gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores

-

-[FixedPcd]

-  gArmTokenSpaceGuid.PcdFvBaseAddress

-  gArmTokenSpaceGuid.PcdFvSize

-  gArmTokenSpaceGuid.PcdVFPEnabled

-

-  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase

-  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize

-  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize

-

-  gArmTokenSpaceGuid.PcdGicDistributorBase

-  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase

-  gArmTokenSpaceGuid.PcdGicSgiIntId

-

-  gEfiMdeModulePkgTokenSpaceGuid.PcdInitValueInTempStack