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| author | Ard Biesheuvel <ardb@kernel.org> | 2022-07-01 20:24:26 +0200 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-10-24 14:30:33 +0000 |
| commit | fb493ac84ebc6860e1690770fb88183effadebfb (patch) | |
| tree | 24b1b8ae1e97d7a15b13b989cd0d08f72c898cf7 /ArmPlatformPkg | |
| parent | b28acb22e019c4a86b9a20f601985219559c91b0 (diff) | |
| download | edk2-fb493ac84ebc6860e1690770fb88183effadebfb.tar.gz edk2-fb493ac84ebc6860e1690770fb88183effadebfb.tar.bz2 edk2-fb493ac84ebc6860e1690770fb88183effadebfb.zip | |
ArmPlatformPkg/PrePeiCore: permit entry with the MMU enabled
Some platforms may set up a preliminary ID map in flash and enter EFI
with the MMU and caches enabled, as this removes a lot of the complexity
around cache coherency. Let's take this into account, and avoid touching
the MMU controls or perform cache invalidation when the MMU is enabled
at entry.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
Diffstat (limited to 'ArmPlatformPkg')
| -rw-r--r-- | ArmPlatformPkg/PrePeiCore/PrePeiCore.c | 24 |
1 files changed, 13 insertions, 11 deletions
diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c index 9c4b25df95..8b86c6e69a 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c @@ -58,17 +58,19 @@ CEntryPoint ( IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint
)
{
- // Data Cache enabled on Primary core when MMU is enabled.
- ArmDisableDataCache ();
- // Invalidate instruction cache
- ArmInvalidateInstructionCache ();
- // Enable Instruction Caches on all cores.
- ArmEnableInstructionCache ();
-
- InvalidateDataCacheRange (
- (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),
- PcdGet32 (PcdCPUCorePrimaryStackSize)
- );
+ if (!ArmMmuEnabled ()) {
+ // Data Cache enabled on Primary core when MMU is enabled.
+ ArmDisableDataCache ();
+ // Invalidate instruction cache
+ ArmInvalidateInstructionCache ();
+ // Enable Instruction Caches on all cores.
+ ArmEnableInstructionCache ();
+
+ InvalidateDataCacheRange (
+ (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),
+ PcdGet32 (PcdCPUCorePrimaryStackSize)
+ );
+ }
//
// Note: Doesn't have to Enable CPU interface in non-secure world,
|