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| author | Abner Chang <abner.chang@hpe.com> | 2020-04-03 13:51:12 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-05-07 03:17:15 +0000 |
| commit | e6956d0052a79dd7d45dd633d8201bce8c34bccd (patch) | |
| tree | e3590c272bbd145b1e6c22d6b5a3d3ad290c9d30 /BaseTools/Source/Python/AutoGen/BuildEngine.py | |
| parent | 722da9078eb03317f23d61f33f8f1f3e1dd78396 (diff) | |
| download | edk2-e6956d0052a79dd7d45dd633d8201bce8c34bccd.tar.gz edk2-e6956d0052a79dd7d45dd633d8201bce8c34bccd.tar.bz2 edk2-e6956d0052a79dd7d45dd633d8201bce8c34bccd.zip | |
.pytool: Add RISC-V architecture on RISC-V EDK2 CI.
BZ:2562:
https://bugzilla.tianocore.org/show_bug.cgi?id=2562
Add RISC-V architecture on RISC-V EDK2 CI testing.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Sean Brogan <sean.brogan@microsoft.com>
Cc: Bret Barkelew <Bret.Barkelew@microsoft.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Cc: Daniel Helmut Schaefer <daniel.schaefer@hpe.com>
Diffstat (limited to 'BaseTools/Source/Python/AutoGen/BuildEngine.py')
0 files changed, 0 insertions, 0 deletions