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| author | Yanbo Huang <yanbo.huang@intel.com> | 2024-07-05 18:17:57 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2024-07-05 17:55:48 +0000 |
| commit | f8bf46be599a957d9374b513f730243725637127 (patch) | |
| tree | 06934ddfdfdc402086366da5108da3b1d0880d63 /BaseTools/Source/Python/Common/Uefi/Capsule/FmpCapsuleHeader.py | |
| parent | 4efcd654ecd94b91bd45da79583f114a0fa12a87 (diff) | |
| download | edk2-f8bf46be599a957d9374b513f730243725637127.tar.gz edk2-f8bf46be599a957d9374b513f730243725637127.tar.bz2 edk2-f8bf46be599a957d9374b513f730243725637127.zip | |
UefiCpuPkg/PiSmmCpuDxeSmm: Consume PcdCpuSmmApSyncTimeout2
This patch is to consume the PcdCpuSmmApSyncTimeout2 to
enhance the flexibility of timeout configuration.
In some cases, certain processors may not be able to enter
SMI, and prolonged waiting could lead to kernel soft/hard
lockup. We have now defined two timeouts. The first timeout
can be set to a smaller value to reduce the waiting period.
Processors that are unable to enter SMI will be woken up
through SMIIPL to enter SMI, followed by a second waiting
period. The second timeout can be set to a larger value to
prevent delays in processors entering SMI case due to the
long instruction execution.
This patch adjust the location of PcdCpuSmmApSyncTimeout2
to avoid conflict.
Signed-off-by: Yanbo Huang <yanbo.huang@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Diffstat (limited to 'BaseTools/Source/Python/Common/Uefi/Capsule/FmpCapsuleHeader.py')
0 files changed, 0 insertions, 0 deletions