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| author | Dhaval <dhaval@rivosinc.com> | 2024-06-20 17:47:18 +0530 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2024-07-15 04:05:56 +0000 |
| commit | 91226e1eecacac832e5091d6a1867dc52666ee85 (patch) | |
| tree | 17376ae411f1e27fc16fe8d2c3e5b4086f4dd228 /BaseTools/Source/Python/Ecc | |
| parent | b54bc983c6102a59c9e0472dd0406ac9ccbaa0bf (diff) | |
| download | edk2-91226e1eecacac832e5091d6a1867dc52666ee85.tar.gz edk2-91226e1eecacac832e5091d6a1867dc52666ee85.tar.bz2 edk2-91226e1eecacac832e5091d6a1867dc52666ee85.zip | |
OvmfPkg/RiscVVirt: Configure zkr PCD for Virt
Keep ZKR feature disabled by default until HW supports
it. Feature is implemented in RISC-V BaseRngLib.
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
Co-authored-by: Tim Wawrzynczak <tim@rivosinc.com>
Diffstat (limited to 'BaseTools/Source/Python/Ecc')
0 files changed, 0 insertions, 0 deletions