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author | Hao Wu <hao.a.wu@intel.com> | 2017-09-19 16:11:29 +0800 |
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committer | Hao Wu <hao.a.wu@intel.com> | 2017-09-29 16:14:17 +0800 |
commit | 27daa8658e518902bf281b07993c2d60af1913c3 (patch) | |
tree | 6d36cfd68d6cd6ef4d65c74ea507c6aaee1e1d19 /BaseTools/Source/Python/GenFds/FdfParser.py | |
parent | bd42d976d510ab56e862b7bf764b1f9e9b19337e (diff) | |
download | edk2-27daa8658e518902bf281b07993c2d60af1913c3.tar.gz edk2-27daa8658e518902bf281b07993c2d60af1913c3.tar.bz2 edk2-27daa8658e518902bf281b07993c2d60af1913c3.zip |
MdeModulePkg/AtaAtapiPassThru: Fix possible out of range left shift
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=699
Within function AhciModeInitialization(), left shift operations of 'BIT0'
in the following statements:
"if ((PortImplementBitMap & (BIT0 << Port)) != 0) {"
will incur possible out of range left shift when Port is 31, since
"1 << 31" is possible to exceed the range of type 'int' (signed).
According to the C11 spec, Section 6.5.7:
> 4 The result of E1 << E2 is E1 left-shifted E2 bit positions; vacated
> bits are filled with zeros. If E1 has an unsigned type, the value
> of the result is E1 * 2^E2 , reduced modulo one more than the
> maximum value representable in the result type. If E1 has a signed
> type and nonnegative value, and E1 * 2^E2 is representable in the
> result type, then that is the resulting value; otherwise, the
> behavior is undefined.
This commit explicitly cast 'BIT0' with UINT32 to resolve this issue.
Cc: Steven Shi <steven.shi@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/GenFds/FdfParser.py')
0 files changed, 0 insertions, 0 deletions