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| author | Sunil V L <sunilvl@ventanamicro.com> | 2021-07-10 14:31:14 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-07-21 02:12:29 +0000 |
| commit | c32c5911c41fa691a5333e7567003cc124e7ab5f (patch) | |
| tree | 908117ccf2b1211d64f85ca40096118568be840a /Conf | |
| parent | 83b43c4cb17ec8c9fd2bb5843bf66e5961f28c82 (diff) | |
| download | edk2-c32c5911c41fa691a5333e7567003cc124e7ab5f.tar.gz edk2-c32c5911c41fa691a5333e7567003cc124e7ab5f.tar.bz2 edk2-c32c5911c41fa691a5333e7567003cc124e7ab5f.zip | |
BaseTools GenFw: Add support for R_RISCV_PCREL_LO12_S relocation
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3459
This patch adds support for R_RISCV_PCREL_LO12_S relocation type.
The logic is same as existing R_RISCV_PCREL_LO12_I relocation
except the difference between load vs store instruction formats.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Pete Batard <pete@akeo.ie>
Cc: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Acked-by: Abner Chang <abner.chang@hpe.com>
Acked-by: Liming Gao <gaoliming@byosoft.com.cn>
Diffstat (limited to 'Conf')
0 files changed, 0 insertions, 0 deletions