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authorHeyi Guo <heyi.guo@linaro.org>2018-02-28 10:19:28 +0800
committerArd Biesheuvel <ard.biesheuvel@linaro.org>2018-03-15 08:25:56 +0000
commit6a9e59a1bc40603fa8d9b25a406ea9bd5fe63915 (patch)
tree5141ae7d69223c330fb0d6dfc2d392ea961b0826 /CorebootPayloadPkg
parentac9b530e6b47c0957345e421b618d8bdd2bf21cf (diff)
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CorebootPayloadPkg/PciHostBridgeLib: clear aperture vars for (re)init
Use ZeroMem() to initialize (or re-initialize) all fields in temporary PCI_ROOT_BRIDGE_APERTURE variables to zero. This is not mandatory but helpful for future extension: when we add new fields to PCI_ROOT_BRIDGE_APERTURE and the default value of these fields can safely be zero, this code will not suffer from an additional change. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Signed-off-by: Yi Li <phoenix.liyi@huawei.com> Reviewed-by: Ni Ruiyu <ruiyu.ni@intel.com> Reviewed-by: Benjamin You <benjamin.you@intel.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Diffstat (limited to 'CorebootPayloadPkg')
-rw-r--r--CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
index 6d94ff72c9..18dcbafdf0 100644
--- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
+++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
@@ -328,8 +328,13 @@ ScanForRootBridges (
for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {
SubBus = PrimaryBus;
Attributes = 0;
+
+ ZeroMem (&Io, sizeof (Io));
+ ZeroMem (&Mem, sizeof (Mem));
+ ZeroMem (&MemAbove4G, sizeof (MemAbove4G));
+ ZeroMem (&PMem, sizeof (PMem));
+ ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G));
Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64;
- Io.Limit = Mem.Limit = MemAbove4G.Limit = PMem.Limit = PMemAbove4G.Limit = 0;
//
// Scan all the PCI devices on the primary bus of the PCI root bridge
//