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| author | Daniil Egranov <daniil.egranov@arm.com> | 2017-10-27 00:33:23 -0500 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-10-27 13:53:27 +0100 |
| commit | 050d513bacec9999f9f3e9eeb558ead37d74c2ab (patch) | |
| tree | 5fcff71c052976ac6b5fa1ab1c6075215a431d20 /EmbeddedPkg/Drivers | |
| parent | 8512fc5731df2268227e61f3fe220a1f96929a4b (diff) | |
| download | edk2-050d513bacec9999f9f3e9eeb558ead37d74c2ab.tar.gz edk2-050d513bacec9999f9f3e9eeb558ead37d74c2ab.tar.bz2 edk2-050d513bacec9999f9f3e9eeb558ead37d74c2ab.zip | |
Drivers/SataSiI3132Dxe: Fixed PCI IO read and write operations
The ATA pass through read should use PCI IO bus master write operation
and ATA pass through write should use PCI IO bus master read operation
as the read and write operations are executed from the bus master's
point of view.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Daniil Egranov <daniil.egranov@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Diffstat (limited to 'EmbeddedPkg/Drivers')
| -rw-r--r-- | EmbeddedPkg/Drivers/SataSiI3132Dxe/SiI3132AtaPassThru.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/EmbeddedPkg/Drivers/SataSiI3132Dxe/SiI3132AtaPassThru.c b/EmbeddedPkg/Drivers/SataSiI3132Dxe/SiI3132AtaPassThru.c index 2fb5fd68db..a938563ebd 100644 --- a/EmbeddedPkg/Drivers/SataSiI3132Dxe/SiI3132AtaPassThru.c +++ b/EmbeddedPkg/Drivers/SataSiI3132Dxe/SiI3132AtaPassThru.c @@ -104,7 +104,7 @@ SiI3132AtaPassThruCommand ( }
Status = PciIo->Map (
- PciIo, EfiPciIoOperationBusMasterRead,
+ PciIo, EfiPciIoOperationBusMasterWrite,
Packet->InDataBuffer, &InDataBufferLength, &PhysInDataBuffer, &PciAllocMapping
);
if (EFI_ERROR (Status)) {
@@ -139,7 +139,7 @@ SiI3132AtaPassThruCommand ( OutDataBufferLength = Packet->OutTransferLength * SataDevice->BlockSize;
Status = PciIo->Map (
- PciIo, EfiPciIoOperationBusMasterWrite,
+ PciIo, EfiPciIoOperationBusMasterRead,
Packet->OutDataBuffer, &OutDataBufferLength, &PhysOutDataBuffer, &PciAllocMapping
);
if (EFI_ERROR (Status)) {
|