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| author | Chasel, Chiu <chasel.chiu@intel.com> | 2018-10-19 17:10:30 +0800 |
|---|---|---|
| committer | Chasel, Chiu <chasel.chiu@intel.com> | 2018-10-25 17:01:36 +0800 |
| commit | b1cc6f672f3b924cdb190e5b92db3b47f46a8911 (patch) | |
| tree | 6422a8a03f085dcbec590ef45193af008d1bcaaf /IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | |
| parent | 5061efe70d020a6811788de2408531f661ef1e45 (diff) | |
| download | edk2-b1cc6f672f3b924cdb190e5b92db3b47f46a8911.tar.gz edk2-b1cc6f672f3b924cdb190e5b92db3b47f46a8911.tar.bz2 edk2-b1cc6f672f3b924cdb190e5b92db3b47f46a8911.zip | |
IntelFsp2Pkg: FSP should not override IDT
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1265
FSP should not override IDT table when it is initialized
by boot loader. IDT should be re-initialized in FSP only
when it is invalid.
To mitigate temporary memory usage a PCD
PcdFspMaxInterruptSupported created for platform to decide
how many interrupts the FSP IDT table can support.
Test: Verified on internal platform and boots successfully.
Cc: Jiewen Yao <Jiewen.yao@intel.com>
Cc: Desimone Nathaniel L <nathaniel.l.desimone@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
Diffstat (limited to 'IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf')
| -rw-r--r-- | IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf index c61af10b8a..dafe6f5993 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf @@ -62,6 +62,7 @@ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES
gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES
gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported ## CONSUMES
[Ppis]
gEfiTemporaryRamSupportPpiGuid ## PRODUCES
|