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| author | Cosmo Lai <cosmo.lai@intel.com> | 2020-10-22 10:51:27 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-10-27 06:06:03 +0000 |
| commit | 31e97bdae2c66e28c5c7df1340757304e1b76d41 (patch) | |
| tree | a3948d998f9422623764c57b69828c6a2c8f7622 /IntelFsp2Pkg/FspSecCore | |
| parent | a3212009d95bbcba7d08076aba2eee51eb1f8e7c (diff) | |
| download | edk2-31e97bdae2c66e28c5c7df1340757304e1b76d41.tar.gz edk2-31e97bdae2c66e28c5c7df1340757304e1b76d41.tar.bz2 edk2-31e97bdae2c66e28c5c7df1340757304e1b76d41.zip | |
IntelFsp2Pkg/FspSecCore: LoadMicrocodeDefault() failed with padding in FV.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3017
Platform microcode FV may have padding between each version of microcode
binary, and current FSP-T/LoadMicrocodeDefault() cannot handle this case
and return not_found unexpectedly.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Signed-off-by: Cosmo Lai <cosmo.lai@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Diffstat (limited to 'IntelFsp2Pkg/FspSecCore')
| -rw-r--r-- | IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm index 7934eab6d7..7fd3d6d843 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -307,10 +307,6 @@ AdvanceFixedSize: add esi, dword 1024
CheckAddress:
- ; Is valid Microcode start point ?
- cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh
- jz Done
-
; Check UPD header revision
cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
jae Fsp22UpdHeader1
@@ -341,6 +337,10 @@ Fsp22UpdHeader1: jmp CheckMainHeader
LoadMicrocodeDefault4:
+ ; Is valid Microcode start point ?
+ cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh
+ jz Done
+
LoadCheck:
; Get the revision of the current microcode update loaded
mov ecx, MSR_IA32_BIOS_SIGN_ID
|