diff options
| author | Chasel Chiu <chasel.chiu@intel.com> | 2023-03-31 00:09:27 -0700 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-04-04 16:39:41 +0000 |
| commit | af98f1fb0311d8e3cc52ab9fc544a8c8ff8f7546 (patch) | |
| tree | 7314a714b88f4bf54d37ab4a90a7b25bef32b710 /IntelFsp2Pkg/FspSecCore | |
| parent | fb89f62d2702faf7db7f7afef342467d4f0fba3c (diff) | |
| download | edk2-af98f1fb0311d8e3cc52ab9fc544a8c8ff8f7546.tar.gz edk2-af98f1fb0311d8e3cc52ab9fc544a8c8ff8f7546.tar.bz2 edk2-af98f1fb0311d8e3cc52ab9fc544a8c8ff8f7546.zip | |
IntelFsp2Pkg: TempRamInit API should preserve EBX/RBX register.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4395
FSP specification defines the TempRamInit API preserved register list
which including EBX/RBX, however current implementation unexpectedly
overriding EBX/RBX register that should be fixed.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Diffstat (limited to 'IntelFsp2Pkg/FspSecCore')
| -rw-r--r-- | IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc index a222f2e376..016f943b43 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc @@ -157,6 +157,9 @@ NextAddress: ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
; whether the processor supports SSE instruction.
;
+ ; Save EBX to MM2
+ ;
+ movd mm2, ebx
mov eax, 1
cpuid
bt edx, 25
@@ -169,6 +172,10 @@ NextAddress: bt ecx, 19
jnc SseError
%endif
+ ;
+ ; Restore EBX from MM2
+ ;
+ movd ebx, mm2
;
; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
|