Revert "FmpDevicePkg: Fix various typos"

This reverts commit f527942e6bdd9f198db90f2de99a0482e9be5b1b.
Commit message was incorrect.

Signed-off-by: Cœur <coeur@gmx.fr>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>

7 files changed, 13 insertions, 13 deletions

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
index e7261b41cd..f14c18c7b9 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
@@ -194,9 +194,9 @@ StackSetupDone:
 

   ;

   ; Pass BFV into the PEI Core

-  ; It uses relative address to calculate the actual boot FV base

+  ; It uses relative address to calucate the actual boot FV base

   ; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and

-  ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs,

+  ; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs,

   ; they are different. The code below can handle both cases.

   ;

   call    ASM_PFX(AsmGetFspBaseAddress)

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm
index ebc91c41e4..e1886ea11b 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm
@@ -1,6 +1,6 @@
 ;------------------------------------------------------------------------------

 ;

-; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>

 ; SPDX-License-Identifier: BSD-2-Clause-Patent

 ;

 ; Abstract:

@@ -46,7 +46,7 @@ ASM_PFX(InitializeFloatingPointUnits):
     fldcw    [ASM_PFX(mFpuControlWord)]

 

     ;

-    ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test

+    ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test

     ; whether the processor supports SSE instruction.

     ;

     mov     eax, 1

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
index 4c321cbece..b257deb76c 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
@@ -1,6 +1,6 @@
 ;------------------------------------------------------------------------------

 ;

-; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>

 ; SPDX-License-Identifier: BSD-2-Clause-Patent

 ;

 ; Abstract:

@@ -150,7 +150,7 @@ NextAddress:
             fldcw   [FpuControlWord]

 

             ;

-            ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test

+            ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test

             ; whether the processor supports SSE instruction.

             ;

             mov     eax, 1

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm
index 5a7e27c240..d72212ed45 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm
@@ -1,6 +1,6 @@
 ;------------------------------------------------------------------------------

 ;

-; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>

 ; SPDX-License-Identifier: BSD-2-Clause-Patent

 ;

 ; Abstract:

@@ -58,7 +58,7 @@ ASM_PFX(SecSwitchStack):
     mov   esp, eax                     ; From now, esp is pointed to permanent memory

 

     ;

-    ; Fixup the ebp point to permanent memory

+    ; Fixup the ebp point to permenent memory

     ;

     mov   eax, ebp

     sub   eax, ebx

diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/SecFsp.c
index 446d1730e9..6497c88ebe 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFsp.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c
@@ -1,6 +1,6 @@
 /** @file

 

-  Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>

+  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>

   SPDX-License-Identifier: BSD-2-Clause-Patent

 

 **/

@@ -169,7 +169,7 @@ FspGlobalDataInit (
   SerialPortInitialize ();

 

   //

-  // Ensure the global data pointer is valid

+  // Ensure the golbal data pointer is valid

   //

   ASSERT (GetFspGlobalDataPointer () == PeiFspData);

 

diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c b/IntelFsp2Pkg/FspSecCore/SecMain.c
index a63d1336e4..cd3ab46ce2 100644
--- a/IntelFsp2Pkg/FspSecCore/SecMain.c
+++ b/IntelFsp2Pkg/FspSecCore/SecMain.c
@@ -110,7 +110,7 @@ SecStartup (
   // |-------------------|---->

   // |                   |

   // |                   |

-  // |      Heap         |    PeiTemporaryRamSize

+  // |      Heap         |    PeiTemporayRamSize

   // |                   |

   // |                   |

   // |-------------------|---->  TempRamBase

diff --git a/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 b/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16
index c519874809..f25de0206a 100644
--- a/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16
+++ b/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16
@@ -2,7 +2,7 @@
 ;  Reset Vector Data structure

 ;  This structure is located at 0xFFFFFFC0

 ;

-; Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>

+; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>

 ; SPDX-License-Identifier: BSD-2-Clause-Patent

 ;

 ;;

@@ -61,7 +61,7 @@ ApStartup:
     ;

     ; Jmp Rel16 instruction

     ; Use machine code directly in case of the assembler optimization

-    ; SEC entry point relative address will be fixed up by some build tool.

+    ; SEC entry point relatvie address will be fixed up by some build tool.

     ;

     ; Typically, SEC entry point is the function _ModuleEntryPoint() defined in

     ; SecEntry.asm