Add IntelFsp2Pkg and IntelFsp2WrapperPkg.

Add FSP2.0 support.
This series of patch is to support FSP2.0 specification at
https://firmware.intel.com/sites/default/files/FSP_EAS_v2.0_Draft%20External.pdf

Some major updates include:
1) One FSP binary is separated to multiple components:
FSP-T, FSP-M, FSP-S, and optional FSP-O.
Each component has its own configuration data region.
2) All FSP-APIs use same UPD format - FSP_UPD_HEADER.
3) Add EnumInitPhaseEndOfFirmware notifyphase.
4) FSP1.1/FSP1.0 compatibility is NOT maintained.
5) We also add rename Fsp* to FspWrapper* in IntelFsp2WrapperPkg,
to indicate that it is for FspWrapper only.

IntelFspPkg and IntelFspWrapperPkg will be deprecated.
The new Intel platform will follow FSP2.0 and use IntelFsp2Pkg
and IntelFsp2WrapperPkg.
The old platform can still use IntelFspPkg and IntelFspWrapperPkg
for compatibility consideration.

Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Ravi P Rangarajan <ravi.p.rangarajan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Ravi P Rangarajan <ravi.p.rangarajan@intel.com>

1 files changed, 140 insertions, 0 deletions

diff --git a/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/PeiCoreEntry.asm b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/PeiCoreEntry.asm
new file mode 100644
index 0000000000..cd1c7b8c5d
--- /dev/null
+++ b/IntelFsp2WrapperPkg/Library/SecFspWrapperPlatformSecLibSample/Ia32/PeiCoreEntry.asm
@@ -0,0 +1,140 @@
+;------------------------------------------------------------------------------

+;

+; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>

+; This program and the accompanying materials

+; are licensed and made available under the terms and conditions of the BSD License

+; which accompanies this distribution.  The full text of the license may be found at

+; http://opensource.org/licenses/bsd-license.php.

+;

+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+;

+; Module Name:

+;

+;  PeiCoreEntry.asm

+;

+; Abstract:

+;

+;   Find and call SecStartup

+;

+;------------------------------------------------------------------------------

+

+.686p

+.xmm

+.model flat, c

+.code

+

+EXTRN   SecStartup:NEAR

+EXTRN   PlatformInit:NEAR

+

+CallPeiCoreEntryPoint   PROC PUBLIC

+  ;

+  ; Obtain the hob list pointer

+  ;

+  mov     eax, [esp+4]

+  ;

+  ; Obtain the stack information

+  ;   ECX: start of range

+  ;   EDX: end of range

+  ;

+  mov     ecx, [esp+8]

+  mov     edx, [esp+0Ch]

+

+  ;

+  ; Platform init

+  ;

+  pushad

+  push edx

+  push ecx

+  push eax

+  call PlatformInit

+  pop  eax

+  pop  eax

+  pop  eax

+  popad

+

+  ;

+  ; Set stack top pointer

+  ;

+  mov     esp, edx

+

+  ;

+  ; Push the hob list pointer

+  ;

+  push    eax

+

+  ;

+  ; Save the value

+  ;   ECX: start of range

+  ;   EDX: end of range

+  ;

+  mov     ebp, esp

+  push    ecx

+  push    edx

+

+  ;

+  ; Push processor count to stack first, then BIST status (AP then BSP)

+  ;

+  mov     eax, 1

+  cpuid

+  shr     ebx, 16

+  and     ebx, 0000000FFh

+  cmp     bl, 1

+  jae     PushProcessorCount

+

+  ;

+  ; Some processors report 0 logical processors.  Effectively 0 = 1.

+  ; So we fix up the processor count

+  ;

+  inc     ebx

+

+PushProcessorCount:

+  push    ebx

+

+  ;

+  ; We need to implement a long-term solution for BIST capture.  For now, we just copy BSP BIST

+  ; for all processor threads

+  ;

+  xor     ecx, ecx

+  mov     cl, bl

+PushBist:

+  movd    eax, mm0

+  push    eax

+  loop    PushBist

+

+  ; Save Time-Stamp Counter

+  movd eax, mm5

+  push eax

+

+  movd eax, mm6

+  push eax

+

+  ;

+  ; Pass entry point of the PEI core

+  ;

+  mov     edi, 0FFFFFFE0h

+  push    DWORD PTR ds:[edi]

+

+  ;

+  ; Pass BFV into the PEI Core

+  ;

+  mov     edi, 0FFFFFFFCh

+  push    DWORD PTR ds:[edi]

+

+  ;

+  ; Pass stack size into the PEI Core

+  ;

+  mov     ecx, [ebp - 4]

+  mov     edx, [ebp - 8]

+  push    ecx       ; RamBase

+

+  sub     edx, ecx

+  push    edx       ; RamSize

+

+  ;

+  ; Pass Control into the PEI Core

+  ;

+  call SecStartup

+CallPeiCoreEntryPoint   ENDP

+

+END