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| author | Yao, Jiewen <jiewen.yao@intel.com> | 2015-02-12 07:02:43 +0000 |
|---|---|---|
| committer | jyao1 <jyao1@Edk2> | 2015-02-12 07:02:43 +0000 |
| commit | 95c95ac0efb10fe4b608a3388d928eb947c15085 (patch) | |
| tree | f3c493443dfe606a7d2c5c991c7e1d75b177c92f /IntelFspWrapperPkg | |
| parent | 4701d96534f2228b6f4aa925606566d2c2bb55be (diff) | |
| download | edk2-95c95ac0efb10fe4b608a3388d928eb947c15085.tar.gz edk2-95c95ac0efb10fe4b608a3388d928eb947c15085.tar.bz2 edk2-95c95ac0efb10fe4b608a3388d928eb947c15085.zip | |
Fsp1.1 update.
Update ApiEntry.asm to use MACRO instead of direct XMM access.
Add sanity parameter check for FSP API.
Add sanity return code check for internal API.
Call LoadUcode before CarInit to meet silicon requirement.
Remove unnecessary VpdBase for PatchTable.
Add ASSERT for NULL check FSP1.1 entrypoint.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Rangarajan, Ravi P" <ravi.p.rangarajan@intel.com>
Reviewed-by: "Ma, Maurice" <maurice.ma@intel.com>
Reviewed-by: "Mudusuru, Giri P" <giri.p.mudusuru@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16834 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'IntelFspWrapperPkg')
| -rw-r--r-- | IntelFspWrapperPkg/FspInitPei/FspInitPei.c | 16 | ||||
| -rw-r--r-- | IntelFspWrapperPkg/FspInitPei/FspInitPeiV2.c | 2 |
2 files changed, 12 insertions, 6 deletions
diff --git a/IntelFspWrapperPkg/FspInitPei/FspInitPei.c b/IntelFspWrapperPkg/FspInitPei/FspInitPei.c index 17a646836a..48a030709b 100644 --- a/IntelFspWrapperPkg/FspInitPei/FspInitPei.c +++ b/IntelFspWrapperPkg/FspInitPei/FspInitPei.c @@ -42,17 +42,21 @@ FspPeiEntryPoint ( return EFI_DEVICE_ERROR;
}
+ ASSERT (FspHeader->TempRamInitEntryOffset != 0);
+ ASSERT (FspHeader->FspInitEntryOffset != 0);
+ ASSERT (FspHeader->NotifyPhaseEntryOffset != 0);
+
if ((PcdGet8 (PcdFspApiVersion) >= 2) &&
(FspHeader->HeaderRevision >= FSP_HEADER_REVISION_2) &&
- (FspHeader->ApiEntryNum >= 6) &&
- (FspHeader->FspMemoryInitEntryOffset != 0) &&
- (FspHeader->TempRamExitEntryOffset != 0) &&
- (FspHeader->FspSiliconInitEntryOffset != 0) ) {
- PcdFspApiVersion = FSP_HEADER_REVISION_2;
+ (FspHeader->ApiEntryNum >= 6) ) {
+ ASSERT (FspHeader->FspMemoryInitEntryOffset != 0);
+ ASSERT (FspHeader->TempRamExitEntryOffset != 0);
+ ASSERT (FspHeader->FspSiliconInitEntryOffset != 0);
+ PcdFspApiVersion = PcdGet8 (PcdFspApiVersion);
}
DEBUG ((DEBUG_INFO, "PcdFspApiVersion - 0x%x\n", PcdFspApiVersion));
- if (PcdFspApiVersion == FSP_HEADER_REVISION_1) {
+ if (PcdFspApiVersion == 1) {
PeiFspInitV1 (FspHeader);
} else {
PeiFspInitV2 (FspHeader);
diff --git a/IntelFspWrapperPkg/FspInitPei/FspInitPeiV2.c b/IntelFspWrapperPkg/FspInitPei/FspInitPeiV2.c index 6ddbf7f1b3..7cad84effb 100644 --- a/IntelFspWrapperPkg/FspInitPei/FspInitPeiV2.c +++ b/IntelFspWrapperPkg/FspInitPei/FspInitPeiV2.c @@ -169,6 +169,7 @@ PeiFspMemoryInit ( FspMemoryInitParams.NvsBufferPtr = GetNvsBuffer ();
DEBUG ((DEBUG_INFO, "NvsBufferPtr - 0x%x\n", FspMemoryInitParams.NvsBufferPtr));
FspMemoryInitParams.RtBufferPtr = (VOID *)&FspRtBuffer;
+ FspHobList = NULL;
FspMemoryInitParams.HobListPtr = &FspHobList;
DEBUG ((DEBUG_INFO, "FspMemoryInitParams - 0x%x\n", &FspMemoryInitParams));
@@ -184,6 +185,7 @@ PeiFspMemoryInit ( ASSERT_EFI_ERROR (Status);
DEBUG ((DEBUG_INFO, " HobListPtr (returned) - 0x%x\n", FspHobList));
+ ASSERT (FspHobList != NULL);
FspHobProcessForMemoryResource (FspHobList);
|