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| author | Tian Feng <feng.tian@intel.com> | 2015-06-16 01:04:47 +0000 |
|---|---|---|
| committer | erictian <erictian@Edk2> | 2015-06-16 01:04:47 +0000 |
| commit | 754b489b46fa2c940f90b4048cc868991cda92a2 (patch) | |
| tree | d8aa9c228199cda661a39ef15ff5b13168b3df93 /MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c | |
| parent | 9c4ae34ebb6b22c83d627a4b976864a8efda8b44 (diff) | |
| download | edk2-754b489b46fa2c940f90b4048cc868991cda92a2.tar.gz edk2-754b489b46fa2c940f90b4048cc868991cda92a2.tar.bz2 edk2-754b489b46fa2c940f90b4048cc868991cda92a2.zip | |
MdeModulePkg/NvmExpressDxe: Add SecurityStorageProtocol support
Produce this protocol for each namespace at NVMe controller.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Tian Feng <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17638 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c | 36 |
1 files changed, 23 insertions, 13 deletions
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c index d37194a910..f9871527dd 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c @@ -433,7 +433,7 @@ NvmExpressPassThru ( // these two cmds are special which requires their data buffer must support simultaneous access by both the
// processor and a PCI Bus Master. It's caller's responsbility to ensure this.
//
- if (((Sq->Opc & (BIT0 | BIT1)) != 0) && (Sq->Opc != NVME_ADMIN_CRIOCQ_OPC) && (Sq->Opc != NVME_ADMIN_CRIOSQ_OPC)) {
+ if (((Sq->Opc & (BIT0 | BIT1)) != 0) && (Sq->Opc != NVME_ADMIN_CRIOCQ_CMD) && (Sq->Opc != NVME_ADMIN_CRIOSQ_CMD)) {
if ((Sq->Opc & BIT0) != 0) {
Flag = EfiPciIoOperationBusMasterRead;
} else {
@@ -567,21 +567,31 @@ NvmExpressPassThru ( }
}
- if ((Private->CqHdbl[QueueType].Cqh ^= 1) == 0) {
- Private->Pt[QueueType] ^= 1;
- }
-
//
- // Copy the Respose Queue entry for this command to the callers response buffer
+ // Check the NVMe cmd execution result
//
- CopyMem(Packet->NvmeCompletion, Cq, sizeof(EFI_NVM_EXPRESS_COMPLETION));
+ if (Status != EFI_TIMEOUT) {
+ if ((Cq->Sct == 0) && (Cq->Sc == 0)) {
+ Status = EFI_SUCCESS;
+ } else {
+ Status = EFI_DEVICE_ERROR;
+ //
+ // Copy the Respose Queue entry for this command to the callers response buffer
+ //
+ CopyMem(Packet->NvmeCompletion, Cq, sizeof(EFI_NVM_EXPRESS_COMPLETION));
+
+ //
+ // Dump every completion entry status for debugging.
+ //
+ DEBUG_CODE_BEGIN();
+ NvmeDumpStatus(Cq);
+ DEBUG_CODE_END();
+ }
+ }
- //
- // Dump every completion entry status for debugging.
- //
- DEBUG_CODE_BEGIN();
- NvmeDumpStatus(Cq);
- DEBUG_CODE_END();
+ if ((Private->CqHdbl[QueueType].Cqh ^= 1) == 0) {
+ Private->Pt[QueueType] ^= 1;
+ }
Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[QueueType]);
PciIo->Mem.Write (
|