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| author | Quan Nguyen <quan@os.amperecomputing.com> | 2020-12-16 20:25:20 +0700 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-12-18 18:09:18 +0000 |
| commit | 0d49b82e4fa5d7eaeb5f73dfb93a932893832437 (patch) | |
| tree | 751d9b3a2701066f7dc49ce900ad7c7bbb1e398b /MdeModulePkg/Bus/Pci/PciSioSerialDxe/Serial.c | |
| parent | e2bfd172e4b98308aadac98f7c8203950a245e4b (diff) | |
| download | edk2-0d49b82e4fa5d7eaeb5f73dfb93a932893832437.tar.gz edk2-0d49b82e4fa5d7eaeb5f73dfb93a932893832437.tar.bz2 edk2-0d49b82e4fa5d7eaeb5f73dfb93a932893832437.zip | |
ArmPkg/ArmGicLib: Add ArmGicSetInterruptPriority() helper function
According to ARM IHI 0069F, section 11.9.18 GICD_IPRIORITYR<n>,
Interrupt Priority Registers, n = 0 - 254, when affinity routing is
enabled for the Security state of an interrupt, GICR_IPRIORITYR<n>
is used instead of GICD_IPRIORITYR<n> where n = 0 to 7 (that is, for
SGIs and PPIs).
As setting interrupt priority for SGIs and PPIs are handled using
difference registers depends on the mode, this patch instroduces
ArmGicSetInterruptPriority() helper function to handle the discrepancy.
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com>
Reviewed-off-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
Diffstat (limited to 'MdeModulePkg/Bus/Pci/PciSioSerialDxe/Serial.c')
0 files changed, 0 insertions, 0 deletions