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| author | Star Zeng <star.zeng@intel.com> | 2017-08-24 17:42:49 +0800 |
|---|---|---|
| committer | Star Zeng <star.zeng@intel.com> | 2017-08-25 17:09:23 +0800 |
| commit | 0b9c0c65400262ee41eb8f4f4d9079fab4777437 (patch) | |
| tree | e8dbad561b0652ead2b1ccf3986616341d89e81f /MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | |
| parent | 9d5dfe9d74fba521011236fb4b0c8c8547e03dda (diff) | |
| download | edk2-0b9c0c65400262ee41eb8f4f4d9079fab4777437.tar.gz edk2-0b9c0c65400262ee41eb8f4f4d9079fab4777437.tar.bz2 edk2-0b9c0c65400262ee41eb8f4f4d9079fab4777437.zip | |
MdeModulePkg XhciDxe: Fix Map and Unmap inconsistency
We found there are loops of *2* Maps and only *1* Unmap and
the DMA buffer address is decreasing.
It is caused by the below code flow.
XhcAsyncInterruptTransfer ->
XhcCreateUrb ->
XhcCreateTransferTrb ->
Map Urb->DataMap (1)
Timer: loops of *2* Maps and only *1* Unmap
XhcMonitorAsyncRequests ->
XhcFlushAsyncIntMap ->
Unmap and Map Urb->DataMap (2)
XhcUpdateAsyncRequest ->
XhcCreateTransferTrb ->
Map Urb->DataMap (3)
This patch is to eliminate (3).
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Diffstat (limited to 'MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c index 6013d7620f..21fdcf130a 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c @@ -259,8 +259,11 @@ XhcCreateTransferTrb ( } else {
EPType = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;
}
-
- if (Urb->Data != NULL) {
+
+ //
+ // No need to remap.
+ //
+ if ((Urb->Data != NULL) && (Urb->DataMap == NULL)) {
if (((UINT8) (Urb->Ep.Direction)) == EfiUsbDataIn) {
MapOp = EfiPciIoOperationBusMasterWrite;
} else {
|