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| author | jdzhang <jdzhang@kunluntech.com.cn> | 2022-09-21 11:05:40 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-09-27 02:44:24 +0000 |
| commit | b3dd9cb836e2aed68198aa79a1ca6afdb25adf80 (patch) | |
| tree | 3766ccd0eede000dbc02060c6a884d2ed59c7706 /MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | |
| parent | 96f3efbd991db83c608909c1c861a77fe26982f1 (diff) | |
| download | edk2-b3dd9cb836e2aed68198aa79a1ca6afdb25adf80.tar.gz edk2-b3dd9cb836e2aed68198aa79a1ca6afdb25adf80.tar.bz2 edk2-b3dd9cb836e2aed68198aa79a1ca6afdb25adf80.zip | |
MdeModulePkg/XhciDxe: Input context update for Evaluate Context command
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4074
Update XhcEvaluateContext/XhcEvaluateContext64 to properly initialize the
input context for Evaluate Context command.
Signed-off-by: jdzhang <jdzhang@kunluntech.com.cn>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Diffstat (limited to 'MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c index c2906e06fd..4ae0297607 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c @@ -3957,6 +3957,7 @@ XhcEvaluateContext ( CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;
EVT_TRB_COMMAND_COMPLETION *EvtTrb;
INPUT_CONTEXT *InputContext;
+ DEVICE_CONTEXT *OutputContext;
EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
@@ -3964,11 +3965,15 @@ XhcEvaluateContext ( //
// 4.6.7 Evaluate Context
//
- InputContext = Xhc->UsbDevContext[SlotId].InputContext;
+ InputContext = Xhc->UsbDevContext[SlotId].InputContext;
+ OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
ZeroMem (InputContext, sizeof (INPUT_CONTEXT));
+ CopyMem (&InputContext->EP[0], &OutputContext->EP[0], sizeof (ENDPOINT_CONTEXT));
+
InputContext->InputControlContext.Dword2 |= BIT1;
InputContext->EP[0].MaxPacketSize = MaxPacketSize;
+ InputContext->EP[0].EPState = 0;
ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT));
@@ -4013,6 +4018,7 @@ XhcEvaluateContext64 ( CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;
EVT_TRB_COMMAND_COMPLETION *EvtTrb;
INPUT_CONTEXT_64 *InputContext;
+ DEVICE_CONTEXT_64 *OutputContext;
EFI_PHYSICAL_ADDRESS PhyAddr;
ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);
@@ -4020,11 +4026,15 @@ XhcEvaluateContext64 ( //
// 4.6.7 Evaluate Context
//
- InputContext = Xhc->UsbDevContext[SlotId].InputContext;
+ InputContext = Xhc->UsbDevContext[SlotId].InputContext;
+ OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;
ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));
+ CopyMem (&InputContext->EP[0], &OutputContext->EP[0], sizeof (ENDPOINT_CONTEXT_64));
+
InputContext->InputControlContext.Dword2 |= BIT1;
InputContext->EP[0].MaxPacketSize = MaxPacketSize;
+ InputContext->EP[0].EPState = 0;
ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));
PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, InputContext, sizeof (INPUT_CONTEXT_64));
|