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| author | Michael Kubacki <michael.kubacki@microsoft.com> | 2020-04-11 04:02:15 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-04-21 02:20:51 +0000 |
| commit | dc528558c99406c811d19f598c4f3303e8953160 (patch) | |
| tree | 02c61cab901532c18680e00b4426a2316d3967de /MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | |
| parent | 309809455abef8bde99993f157ae5f3b9a1a05f6 (diff) | |
| download | edk2-dc528558c99406c811d19f598c4f3303e8953160.tar.gz edk2-dc528558c99406c811d19f598c4f3303e8953160.tar.bz2 edk2-dc528558c99406c811d19f598c4f3303e8953160.zip | |
MdeModulePkg/XhciDxe: Use BaseLib linked list iteration macros
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1959
Replaces usage of the linked list iteration macros defined in Xhci.h
with the common definition in BaseLib.h.
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Sean Brogan <sean.brogan@microsoft.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Guomin Jiang <guomin.jiang@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
Diffstat (limited to 'MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c index c0c374fc47..ab8957c546 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c @@ -3,6 +3,7 @@ XHCI transfer scheduling routines.
Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
+Copyright (c) Microsoft Corporation.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -1051,7 +1052,7 @@ IsAsyncIntTrb ( LIST_ENTRY *Next;
URB *CheckedUrb;
- EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
+ BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
CheckedUrb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
if (IsTransferRingTrb (Xhc, Trb, CheckedUrb)) {
*Urb = CheckedUrb;
@@ -1346,7 +1347,7 @@ XhciDelAsyncIntTransfer ( Urb = NULL;
- EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
+ BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
if ((Urb->Ep.BusAddr == BusAddr) &&
(Urb->Ep.EpAddr == EpNum) &&
@@ -1386,7 +1387,7 @@ XhciDelAllAsyncIntTransfers ( URB *Urb;
EFI_STATUS Status;
- EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
+ BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
//
@@ -1578,7 +1579,7 @@ XhcMonitorAsyncRequests ( Xhc = (USB_XHCI_INSTANCE*) Context;
- EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
+ BASE_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {
Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);
//
|