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| author | Ruiyu Ni <ruiyu.ni@intel.com> | 2018-09-21 15:20:45 +0800 |
|---|---|---|
| committer | Ruiyu Ni <ruiyu.ni@intel.com> | 2018-09-26 12:12:50 +0800 |
| commit | bff6584d1f0d366ea08fb541ecbe82554f1eaa4e (patch) | |
| tree | 62599e4e51907ea49d6bf1c6522058ab4c9298b6 /MdeModulePkg/Bus/Pci | |
| parent | 666d05a0ade67555a39a2191619e04a838ab2280 (diff) | |
| download | edk2-bff6584d1f0d366ea08fb541ecbe82554f1eaa4e.tar.gz edk2-bff6584d1f0d366ea08fb541ecbe82554f1eaa4e.tar.bz2 edk2-bff6584d1f0d366ea08fb541ecbe82554f1eaa4e.zip | |
MdeModulePkg/PciHostBridge: Fix a bug that prevents PMEM access
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1196
RootBridgeIoCheckParameter() verifies that the requested MMIO access
can fit in any of the MEM/PMEM 32/64 ranges. But today's logic
somehow only checks the requested access against MEM 32/64 ranges.
It should also check the requested access against PMEM 32/64 ranges.
The patch fixes this issue.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.com>
Diffstat (limited to 'MdeModulePkg/Bus/Pci')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c index 2c373e41de..87385aa172 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c @@ -413,12 +413,18 @@ RootBridgeIoCheckParameter ( // By comparing the Address against Limit we know which range to be used
// for checking
//
- if (Address + Length <= RootBridge->Mem.Limit + 1) {
- Base = RootBridge->Mem.Base;
+ if ((Address >= RootBridge->Mem.Base) && (Address + Length <= RootBridge->Mem.Limit + 1)) {
+ Base = RootBridge->Mem.Base;
Limit = RootBridge->Mem.Limit;
- } else {
- Base = RootBridge->MemAbove4G.Base;
+ } else if ((Address >= RootBridge->PMem.Base) && (Address + Length <= RootBridge->PMem.Limit + 1)) {
+ Base = RootBridge->PMem.Base;
+ Limit = RootBridge->PMem.Limit;
+ } else if ((Address >= RootBridge->MemAbove4G.Base) && (Address + Length <= RootBridge->MemAbove4G.Limit + 1)) {
+ Base = RootBridge->MemAbove4G.Base;
Limit = RootBridge->MemAbove4G.Limit;
+ } else {
+ Base = RootBridge->PMemAbove4G.Base;
+ Limit = RootBridge->PMemAbove4G.Limit;
}
} else {
PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;
|