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| author | Sean Brogan <sean.brogan@microsoft.com> | 2019-09-03 16:52:26 -0700 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2019-11-20 02:47:19 +0000 |
| commit | 7607174192166dd5d2d6913fc2fdb8ce539cd3c9 (patch) | |
| tree | c28e164d64ff6d1e89c895b09eb5b5358f6ccd9a /MdeModulePkg/Bus | |
| parent | 0b9ad0bc030bbd79073a26fc9b3527ff9128b9da (diff) | |
| download | edk2-7607174192166dd5d2d6913fc2fdb8ce539cd3c9.tar.gz edk2-7607174192166dd5d2d6913fc2fdb8ce539cd3c9.tar.bz2 edk2-7607174192166dd5d2d6913fc2fdb8ce539cd3c9.zip | |
MdeModulePkg/NvmExpressDxe: Fix wrong queue size for async IO queues
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2118
When a packet is queued/completed for the asynchronous IO queue, the logic
to roll over to the front of the queue doesn't account for actual size of
the IO Submission/Completion queue.
This causes a device to hang due to doorbell being outside of visible
queue. An example would be if an NVMe drive only supported a queue size of
128 while the driver supports 256.
Cc: Jian J Wang <jian.j.wang@intel.com>
Signed-off-by: Sean Brogan <sean.brogan@microsoft.com>
Signed-off-by: Hao A Wu <hao.a.wu@intel.com>
Acked-by: Ray Ni <ray.ni@intel.com>
Diffstat (limited to 'MdeModulePkg/Bus')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c | 2 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c | 6 |
2 files changed, 5 insertions, 3 deletions
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c index 3bde96bc95..62886d5c91 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c @@ -672,7 +672,7 @@ ProcessAsyncTaskList ( }
Private->CqHdbl[QueueId].Cqh++;
- if (Private->CqHdbl[QueueId].Cqh > NVME_ASYNC_CCQ_SIZE) {
+ if (Private->CqHdbl[QueueId].Cqh > MIN (NVME_ASYNC_CCQ_SIZE, Private->Cap.Mqes)) {
Private->CqHdbl[QueueId].Cqh = 0;
Private->Pt[QueueId] ^= 1;
}
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c index 8e72137946..e9357b1239 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressPassthru.c @@ -452,6 +452,7 @@ NvmExpressPassThru ( NVME_SQ *Sq;
NVME_CQ *Cq;
UINT16 QueueId;
+ UINT16 QueueSize;
UINT32 Bytes;
UINT16 Offset;
EFI_EVENT TimerEvent;
@@ -540,6 +541,7 @@ NvmExpressPassThru ( Prp = NULL;
TimerEvent = NULL;
Status = EFI_SUCCESS;
+ QueueSize = MIN (NVME_ASYNC_CSQ_SIZE, Private->Cap.Mqes) + 1;
if (Packet->QueueType == NVME_ADMIN_QUEUE) {
QueueId = 0;
@@ -552,7 +554,7 @@ NvmExpressPassThru ( //
// Submission queue full check.
//
- if ((Private->SqTdbl[QueueId].Sqt + 1) % (NVME_ASYNC_CSQ_SIZE + 1) ==
+ if ((Private->SqTdbl[QueueId].Sqt + 1) % QueueSize ==
Private->AsyncSqHead) {
return EFI_NOT_READY;
}
@@ -701,7 +703,7 @@ NvmExpressPassThru ( //
if ((Event != NULL) && (QueueId != 0)) {
Private->SqTdbl[QueueId].Sqt =
- (Private->SqTdbl[QueueId].Sqt + 1) % (NVME_ASYNC_CSQ_SIZE + 1);
+ (Private->SqTdbl[QueueId].Sqt + 1) % QueueSize;
} else {
Private->SqTdbl[QueueId].Sqt ^= 1;
}
|