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authorDat Mach <dmach@nvidia.com>2024-03-19 14:32:41 -0700
committerLiming Gao <gaoliming@byosoft.com.cn>2024-03-22 12:47:04 +0800
commit7f1ffba5de3d9840dbeeba20fba165f2fb724941 (patch)
tree842bfc9f4b5470c1aae044e9a0a8613be53b9751 /MdeModulePkg/Bus
parent35f6a2780e5198315a9f100c07b3bc86187d20a8 (diff)
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MdeModulePkg/Xhci: Skip another size round up for TRB address
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4560 Commit f36e1ec1f0a5fd3be84913e09181d7813444b620 had fixed the DXE_ASSERT caused by the TRB size round up from 16 to 64 for most cases. However, there is a remaining case that the TRB size is also rounded up during setting TR dequeue pointer that would trigger DXE_ASSERT. This patch sets the alignment flag to FALSE in XhcSetTrDequeuePointer to fix this issue as well. Cc: Gao Cheng <gao.cheng@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Signed-off-by: Dat Mach <dmach@nvidia.com> Reviewed-by: Gao Cheng <gao.cheng@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Diffstat (limited to 'MdeModulePkg/Bus')
-rw-r--r--MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c2
-rw-r--r--MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
index 05528a478b..5d735008ba 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
@@ -3539,7 +3539,7 @@ XhcSetTrDequeuePointer (
// Send stop endpoint command to transit Endpoint from running to stop state
//
ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), TRUE);
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), FALSE);
CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS;
CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdSetTRDeq.CycleBit = 1;
diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
index 53272f62dd..c956e45907 100644
--- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
+++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c
@@ -2526,7 +2526,7 @@ XhcPeiSetTrDequeuePointer (
// Send stop endpoint command to transit Endpoint from running to stop state
//
ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));
- PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), TRUE);
+ PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), FALSE);
CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS;
CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (PhyAddr);
CmdSetTRDeq.CycleBit = 1;