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| author | Tomas Pilar <quic_tpilar@quicinc.com> | 2022-02-24 16:22:19 +0000 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-02-28 10:17:39 +0000 |
| commit | b1b89f9009f2390652e0061bd7b24fc40732bc70 (patch) | |
| tree | db78ab8604fbf46f644899f9135aa08909a0835b /MdeModulePkg/Bus | |
| parent | f1d1c337e7c0575da7fd248b2dd9cffc755940df (diff) | |
| download | edk2-b1b89f9009f2390652e0061bd7b24fc40732bc70.tar.gz edk2-b1b89f9009f2390652e0061bd7b24fc40732bc70.tar.bz2 edk2-b1b89f9009f2390652e0061bd7b24fc40732bc70.zip | |
MdeModulePkg: Correct high-memory use in NvmExpressDxe
Move the logic that stores starting PCI attributes and sets the
EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute to
DriverBindingStart() before the memory that backs the
DMA engine is allocated.
This ensures that the DMA-backing memory is not forcibly allocated
below 4G in system address map. Otherwise the allocation fails on
platforms that do not have any memory below the 4G mark and the drive
initialisation fails.
Leave the PCI device enabling attribute logic in NvmeControllerInit()
to ensure that the device is re-enabled on reset in case it was
disabled via PCI attributes.
Cc: Ray Ni <ray.ni@intel.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Tomas Pilar <quic_tpilar@quicinc.com>
Acked-by: Hao A Wu <hao.a.wu@intel.com>
Diffstat (limited to 'MdeModulePkg/Bus')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c | 27 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c | 26 |
2 files changed, 28 insertions, 25 deletions
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c index 9d40f67e8e..5a1eda8e8d 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c @@ -960,6 +960,33 @@ NvmExpressDriverBindingStart ( }
//
+ // Save original PCI attributes
+ //
+ Status = PciIo->Attributes (
+ PciIo,
+ EfiPciIoAttributeOperationGet,
+ 0,
+ &Private->PciAttributes
+ );
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Enable 64-bit DMA support in the PCI layer.
+ //
+ Status = PciIo->Attributes (
+ PciIo,
+ EfiPciIoAttributeOperationEnable,
+ EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE,
+ NULL
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "NvmExpressDriverBindingStart: failed to enable 64-bit DMA (%r)\n", Status));
+ }
+
+ //
// 6 x 4kB aligned buffers will be carved out of this buffer.
// 1st 4kB boundary is the start of the admin submission queue.
// 2nd 4kB boundary is the start of the admin completion queue.
diff --git a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c index ac77afe113..d87212ffb2 100644 --- a/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c +++ b/MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c @@ -728,22 +728,11 @@ NvmeControllerInit ( UINT8 Mn[41];
//
- // Save original PCI attributes and enable this controller.
+ // Enable this controller.
//
PciIo = Private->PciIo;
Status = PciIo->Attributes (
PciIo,
- EfiPciIoAttributeOperationGet,
- 0,
- &Private->PciAttributes
- );
-
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- Status = PciIo->Attributes (
- PciIo,
EfiPciIoAttributeOperationSupported,
0,
&Supports
@@ -765,19 +754,6 @@ NvmeControllerInit ( }
//
- // Enable 64-bit DMA support in the PCI layer.
- //
- Status = PciIo->Attributes (
- PciIo,
- EfiPciIoAttributeOperationEnable,
- EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE,
- NULL
- );
- if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_WARN, "NvmeControllerInit: failed to enable 64-bit DMA (%r)\n", Status));
- }
-
- //
// Read the Controller Capabilities register and verify that the NVM command set is supported
//
Status = ReadNvmeControllerCapabilities (Private, &Private->Cap);
|