diff options
| author | erictian <erictian@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-11-16 10:24:47 +0000 |
|---|---|---|
| committer | erictian <erictian@6f19259b-4bc3-4df7-8a09-765794883524> | 2011-11-16 10:24:47 +0000 |
| commit | f01219e875c68e045f1bc755390f5e238ba5a4ad (patch) | |
| tree | 760b8e1c6284ea17a54d92f7b2c047fc492435c3 /MdeModulePkg/Bus | |
| parent | 96aace827e120bd6f3d947360d71795e14842508 (diff) | |
| download | edk2-f01219e875c68e045f1bc755390f5e238ba5a4ad.tar.gz edk2-f01219e875c68e045f1bc755390f5e238ba5a4ad.tar.bz2 edk2-f01219e875c68e045f1bc755390f5e238ba5a4ad.zip | |
MdeModulePkg: Enable port power if port power control feature is supported by EHCI
signed-off-by: erictian
reviewed-by: li-elvin
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12725 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdeModulePkg/Bus')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c | 15 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c | 19 | ||||
| -rw-r--r-- | MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h | 3 |
3 files changed, 29 insertions, 8 deletions
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c index 77aba643ab..c141803c38 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c +++ b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c @@ -469,9 +469,12 @@ EhcSetRootHubPortFeature ( case EfiUsbPortPower:
//
- // Not supported, ignore the operation
+ // Set port power bit when PPC is 1
//
- Status = EFI_SUCCESS;
+ if ((Ehc->HcCapParams & HCSP_PPC) == HCSP_PPC) {
+ State |= PORTSC_POWER;
+ EhcWriteOpReg (Ehc, Offset, State);
+ }
break;
case EfiUsbPortOwner:
@@ -598,6 +601,14 @@ EhcClearRootHubPortFeature ( break;
case EfiUsbPortPower:
+ //
+ // Clear port power bit when PPC is 1
+ //
+ if ((Ehc->HcCapParams & HCSP_PPC) == HCSP_PPC) {
+ State &= ~PORTSC_POWER;
+ EhcWriteOpReg (Ehc, Offset, State);
+ }
+ break;
case EfiUsbPortSuspendChange:
case EfiUsbPortResetChange:
//
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c index a79bd48390..252e3d5fa2 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c @@ -2,7 +2,7 @@ The EHCI register operation routines.
-Copyright (c) 2007 - 2009, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -554,6 +554,7 @@ EhcInitHC ( )
{
EFI_STATUS Status;
+ UINT32 Index;
// This ASSERT crashes the BeagleBoard. There is some issue in the USB stack.
// This ASSERT needs to be removed so the BeagleBoard will boot. When we fix
@@ -580,21 +581,29 @@ EhcInitHC ( EhcWriteOpReg (Ehc, EHC_USBINTR_OFFSET, 0);
//
- // 2. Program periodic frame list, already done in EhcInitSched
- // 3. Start the Host Controller
+ // 2. Start the Host Controller
//
EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);
//
- // 4. Set all ports routing to EHC
+ // 3. Power up all ports if EHCI has Port Power Control (PPC) support
//
- EhcSetOpRegBit (Ehc, EHC_CONFIG_FLAG_OFFSET, CONFIGFLAG_ROUTE_EHC);
+ if (Ehc->HcStructParams & HCSP_PPC) {
+ for (Index = 0; Index < (UINT8) (Ehc->HcStructParams & HCSP_NPORTS); Index++) {
+ EhcSetOpRegBit (Ehc, (UINT32) (EHC_PORT_STAT_OFFSET + (4 * Index)), PORTSC_POWER);
+ }
+ }
//
// Wait roothub port power stable
//
gBS->Stall (EHC_ROOT_PORT_RECOVERY_STALL);
+ //
+ // 4. Set all ports routing to EHC
+ //
+ EhcSetOpRegBit (Ehc, EHC_CONFIG_FLAG_OFFSET, CONFIGFLAG_ROUTE_EHC);
+
Status = EhcEnablePeriodSchd (Ehc, EHC_GENERIC_TIMEOUT);
if (EFI_ERROR (Status)) {
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h index 98c2915b45..d1f38d38f0 100644 --- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h +++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h @@ -2,7 +2,7 @@ This file contains the definination for host controller register operation routines.
-Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -32,6 +32,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. // Capability register bit definition
//
#define HCSP_NPORTS 0x0F // Number of root hub port
+#define HCSP_PPC 0x10 // Port Power Control
#define HCCP_64BIT 0x01 // 64-bit addressing capability
//
|