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| author | Edgar Handal <ehandal@nvidia.com> | 2019-02-20 01:06:56 +0800 |
|---|---|---|
| committer | Hao Wu <hao.a.wu@intel.com> | 2019-02-20 09:07:27 +0800 |
| commit | f168816c49e388dcd097dd62d766d63f73aaabb3 (patch) | |
| tree | 4a67cf45d4df3ffc9cb08dff2b7daa9ed843edb4 /MdeModulePkg/Bus | |
| parent | 195f673f6270aaf73dd34b75f1da26451b63c316 (diff) | |
| download | edk2-f168816c49e388dcd097dd62d766d63f73aaabb3.tar.gz edk2-f168816c49e388dcd097dd62d766d63f73aaabb3.tar.bz2 edk2-f168816c49e388dcd097dd62d766d63f73aaabb3.zip | |
MdeModulePkg/SdMmcPciHcDxe: Use 16/32-bit IO widths
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1537
Use 16-bit and 32-bit IO widths for SDMMC MMIO to prevent all register
accesses from being split up into 8-bit accesses.
The SDHCI specification states that the registers shall be accessible in
byte, word, and double word accesses. (SD Host Controller Simplified
Specification 4.20 Section 1.2)
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
Diffstat (limited to 'MdeModulePkg/Bus')
| -rw-r--r-- | MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 25 |
1 files changed, 21 insertions, 4 deletions
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c index 4c64da3b20..d73fa10a35 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c @@ -154,19 +154,36 @@ SdMmcHcRwMmio ( )
{
EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL_WIDTH Width;
if ((PciIo == NULL) || (Data == NULL)) {
return EFI_INVALID_PARAMETER;
}
- if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {
- return EFI_INVALID_PARAMETER;
+ switch (Count) {
+ case 1:
+ Width = EfiPciIoWidthUint8;
+ break;
+ case 2:
+ Width = EfiPciIoWidthUint16;
+ Count = 1;
+ break;
+ case 4:
+ Width = EfiPciIoWidthUint32;
+ Count = 1;
+ break;
+ case 8:
+ Width = EfiPciIoWidthUint32;
+ Count = 2;
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
}
if (Read) {
Status = PciIo->Mem.Read (
PciIo,
- EfiPciIoWidthUint8,
+ Width,
BarIndex,
(UINT64) Offset,
Count,
@@ -175,7 +192,7 @@ SdMmcHcRwMmio ( } else {
Status = PciIo->Mem.Write (
PciIo,
- EfiPciIoWidthUint8,
+ Width,
BarIndex,
(UINT64) Offset,
Count,
|