MdeModulePkg/PiSmmIpl: Do not reset SMRAM to UC when CPU driver runs

Today's PiSmmIpl implementation initially sets SMRAM to WB to speed
up the SMM core/modules loading before SMM CPU driver runs.
When SMM CPU driver runs, PiSmmIpl resets the SMRAM to UC. It's done
in SmmIplDxeDispatchEventNotify(). COMM_BUFFER_SMM_DISPATCH_RESTART
is returned from SMM core that SMM CPU driver is just dispatched.

Since now the SMRR is widely used to control the SMRAM cache setting.
It's not needed to reset the SMRAM to UC anymore.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>

1 files changed, 2 insertions, 13 deletions

diff --git a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c b/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c
index f8cbe1704b..2fb877127b 100644
--- a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c
+++ b/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c
@@ -673,20 +673,9 @@ SmmIplDxeDispatchEventNotify (
     }

 

     //

-    // Attempt to reset SMRAM cacheability to UC

-    // Assume CPU AP is available at this time

-    //

-    Status = gDS->SetMemorySpaceAttributes(

-                    mSmramCacheBase,

-                    mSmramCacheSize,

-                    EFI_MEMORY_UC

-                    );

-    if (EFI_ERROR (Status)) {

-      DEBUG ((DEBUG_WARN, "SMM IPL failed to reset SMRAM window to EFI_MEMORY_UC\n"));

-    }

-

-    //

     // Close all SMRAM ranges to protect SMRAM

+    // NOTE: SMRR is enabled by CPU SMM driver by calling SmmCpuFeaturesInitializeProcessor() from SmmCpuFeaturesLib

+    //       so no need to reset the SMRAM to UC in MTRR.

     //

     Status = mSmmAccess->Close (mSmmAccess);

     ASSERT_EFI_ERROR (Status);