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| author | Ashish Singhal <ashishsingha@nvidia.com> | 2020-01-28 01:52:45 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-02-06 14:46:42 +0000 |
| commit | 7285f275ff5482fb8cbf1ce5f4cd2e4df0a3cc62 (patch) | |
| tree | 2e11112b0e604db81b1533709611d60204a1bebf /MdeModulePkg/Library | |
| parent | 1549651da623aa35c745bd1f283c907324bd6cc9 (diff) | |
| download | edk2-7285f275ff5482fb8cbf1ce5f4cd2e4df0a3cc62.tar.gz edk2-7285f275ff5482fb8cbf1ce5f4cd2e4df0a3cc62.tar.bz2 edk2-7285f275ff5482fb8cbf1ce5f4cd2e4df0a3cc62.zip | |
MdeModulePkg/BaseSerialPortLib16550: Fix Serial Port Ready
Before writing data to FIFO, wait for the serial port to be ready,
to make sure both the transmit FIFO and shift register empty. Code
comment was saying the right thing but code was missing a check.
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
Diffstat (limited to 'MdeModulePkg/Library')
| -rw-r--r-- | MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c index bbae379887..9cb50dd80d 100644 --- a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c +++ b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c @@ -646,7 +646,7 @@ SerialPortWrite ( // Wait for the serial port to be ready, to make sure both the transmit FIFO
// and shift register empty.
//
- while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_TEMT) == 0);
+ while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));
//
// Fill then entire Tx FIFO
|