summaryrefslogtreecommitdiffstats
path: root/MdePkg/Include/IndustryStandard/PciExpress21.h
diff options
context:
space:
mode:
authorRuiyu Ni <ruiyu.ni@intel.com>2017-10-26 16:06:56 +0800
committerRuiyu Ni <ruiyu.ni@intel.com>2017-11-08 12:46:50 +0800
commit400a59737fc3d14b0acc0b0a66a294bb6db894b6 (patch)
treee481b9f5423440232a975c3150ac2306b5e9b6a6 /MdePkg/Include/IndustryStandard/PciExpress21.h
parentcb68247d5c47c5adb667ed7433c6610641edbf95 (diff)
downloadedk2-400a59737fc3d14b0acc0b0a66a294bb6db894b6.tar.gz
edk2-400a59737fc3d14b0acc0b0a66a294bb6db894b6.tar.bz2
edk2-400a59737fc3d14b0acc0b0a66a294bb6db894b6.zip
MdePkg/PciExpress21.h: Fix typo in PCI_REG_PCIE_SLOT_CONTROL
PCI_REG_PCIE_SLOT_CONTROL contains a typo. It is defined as: typedef union { struct { UINT32 AttentionButtonPressed : 1; UINT32 ... ... } Bits; UINT16 Uint16; } PCI_REG_PCIE_SLOT_CONTROL; The bit field data type should be UINT16 instead of UINT32, results sizeof (PCI_REG_PCIE_SLOT_CONTROL) equals to 4 instead of 2. Because this structure is used in PCI_CAPABILITY_PCIEXP as below: typedef struct { ... PCI_REG_PCIE_SLOT_CONTROL SlotControl; PCI_REG_PCIE_SLOT_STATUS SlotStatus; } PCI_CAPABILITY_PCIEXP; It cause the OFFSET_OF (PCI_CAPABILITY_PCIEXP, SlotStatus) equal to a wrong value. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
Diffstat (limited to 'MdePkg/Include/IndustryStandard/PciExpress21.h')
-rw-r--r--MdePkg/Include/IndustryStandard/PciExpress21.h24
1 files changed, 12 insertions, 12 deletions
diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Include/IndustryStandard/PciExpress21.h
index ce9c06a7c6..d90b5975ba 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress21.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress21.h
@@ -182,18 +182,18 @@ typedef union {
typedef union {
struct {
- UINT32 AttentionButtonPressed : 1;
- UINT32 PowerFaultDetected : 1;
- UINT32 MrlSensorChanged : 1;
- UINT32 PresenceDetectChanged : 1;
- UINT32 CommandCompletedInterrupt : 1;
- UINT32 HotPlugInterrupt : 1;
- UINT32 AttentionIndicator : 2;
- UINT32 PowerIndicator : 2;
- UINT32 PowerController : 1;
- UINT32 ElectromechanicalInterlock : 1;
- UINT32 DataLinkLayerStateChanged : 1;
- UINT32 Reserved : 3;
+ UINT16 AttentionButtonPressed : 1;
+ UINT16 PowerFaultDetected : 1;
+ UINT16 MrlSensorChanged : 1;
+ UINT16 PresenceDetectChanged : 1;
+ UINT16 CommandCompletedInterrupt : 1;
+ UINT16 HotPlugInterrupt : 1;
+ UINT16 AttentionIndicator : 2;
+ UINT16 PowerIndicator : 2;
+ UINT16 PowerController : 1;
+ UINT16 ElectromechanicalInterlock : 1;
+ UINT16 DataLinkLayerStateChanged : 1;
+ UINT16 Reserved : 3;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_SLOT_CONTROL;