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| author | Tom Lendacky <thomas.lendacky@amd.com> | 2020-08-12 15:21:35 -0500 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-08-16 16:45:42 +0000 |
| commit | a80e887819ac27800551811e2943181ad811effa (patch) | |
| tree | d74633526cb4fda47ab266e7243eb3a16dfd8cda /MdePkg/Include | |
| parent | c9db7bf10ac3438b532e04bf5b338ff9e4c15344 (diff) | |
| download | edk2-a80e887819ac27800551811e2943181ad811effa.tar.gz edk2-a80e887819ac27800551811e2943181ad811effa.tar.bz2 edk2-a80e887819ac27800551811e2943181ad811effa.zip | |
MdePkg: Add the MSR definition for the GHCB register
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
For SEV-ES, the GHCB page address is stored in the GHCB MSR register
(0xc0010130). Define the register and the format used for register
during GHCB protocol negotiation.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Diffstat (limited to 'MdePkg/Include')
| -rw-r--r-- | MdePkg/Include/Register/Amd/Fam17Msr.h | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h b/MdePkg/Include/Register/Amd/Fam17Msr.h index 6ef45a9b21..e4db09c518 100644 --- a/MdePkg/Include/Register/Amd/Fam17Msr.h +++ b/MdePkg/Include/Register/Amd/Fam17Msr.h @@ -18,6 +18,52 @@ #define __FAM17_MSR_H__
/**
+ Secure Encrypted Virtualization - Encrypted State (SEV-ES) GHCB register
+
+**/
+#define MSR_SEV_ES_GHCB 0xc0010130
+
+/**
+ MSR information returned for #MSR_SEV_ES_GHCB
+**/
+typedef union {
+ struct {
+ UINT32 Function:12;
+ UINT32 Reserved1:20;
+ UINT32 Reserved2:32;
+ } GhcbInfo;
+
+ struct {
+ UINT8 Reserved[3];
+ UINT8 SevEncryptionBitPos;
+ UINT16 SevEsProtocolMin;
+ UINT16 SevEsProtocolMax;
+ } GhcbProtocol;
+
+ struct {
+ UINT32 Function:12;
+ UINT32 ReasonCodeSet:4;
+ UINT32 ReasonCode:8;
+ UINT32 Reserved1:8;
+ UINT32 Reserved2:32;
+ } GhcbTerminate;
+
+ VOID *Ghcb;
+
+ UINT64 GhcbPhysicalAddress;
+} MSR_SEV_ES_GHCB_REGISTER;
+
+#define GHCB_INFO_SEV_INFO 1
+#define GHCB_INFO_SEV_INFO_GET 2
+#define GHCB_INFO_CPUID_REQUEST 4
+#define GHCB_INFO_CPUID_RESPONSE 5
+#define GHCB_INFO_TERMINATE_REQUEST 256
+
+#define GHCB_TERMINATE_GHCB 0
+#define GHCB_TERMINATE_GHCB_GENERAL 0
+#define GHCB_TERMINATE_GHCB_PROTOCOL 1
+
+/**
Secure Encrypted Virtualization (SEV) status register
**/
|