MdePkg: Removing ipf which is no longer supported from edk2.

Removing rules for Ipf sources file:
* Remove the source file which path with "ipf" and also listed in
  [Sources.IPF] section of INF file.
* Remove the source file which listed in [Components.IPF] section
  of DSC file and not listed in any other [Components] section.
* Remove the embedded Ipf code for MDE_CPU_IPF.

Removing rules for Inf file:
* Remove IPF from VALID_ARCHITECTURES comments.
* Remove DXE_SAL_DRIVER from LIBRARY_CLASS in [Defines] section.
* Remove the INF which only listed in [Components.IPF] section in DSC.
* Remove statements from [BuildOptions] that provide IPF specific flags.
* Remove any IPF sepcific sections.

Removing rules for Dec file:
* Remove [Includes.IPF] section from Dec.

Removing rules for Dsc file:
* Remove IPF from SUPPORTED_ARCHITECTURES in [Defines] section of DSC.
* Remove any IPF specific sections.
* Remove statements from [BuildOptions] that provide IPF specific flags.

Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chen A Chen <chen.a.chen@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

3 files changed, 1 insertions, 133 deletions

diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
index 53cb3cf45d..af2f09617a 100644
--- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
@@ -29,7 +29,7 @@
 

 

 #

-#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC ARM AARCH64

+#  VALID_ARCHITECTURES           = IA32 X64 EBC ARM AARCH64

 #

 

 [Sources.IA32]

@@ -51,10 +51,6 @@
   X64/CpuFlushTlb.nasm| GCC

   X64/CpuFlushTlb.S | GCC

 

-[Sources.IPF]

-  Ipf/CpuFlushTlb.s

-  Ipf/CpuSleep.c

-

 [Sources.EBC]

   Ebc/CpuSleepFlushTlb.c

 

@@ -76,7 +72,3 @@
   MdePkg/MdePkg.dec

 

 

-[LibraryClasses.IPF]

-  PalLib

-  BaseLib

-

diff --git a/MdePkg/Library/BaseCpuLib/Ipf/CpuFlushTlb.s b/MdePkg/Library/BaseCpuLib/Ipf/CpuFlushTlb.s
deleted file mode 100644
index 911f7809a0..0000000000
--- a/MdePkg/Library/BaseCpuLib/Ipf/CpuFlushTlb.s
+++ /dev/null
@@ -1,58 +0,0 @@
-/// @file

-///   CpuFlushTlb() function for Itanium-based architecture.

-///

-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>

-/// This program and the accompanying materials

-/// are licensed and made available under the terms and conditions of the BSD License

-/// which accompanies this distribution.  The full text of the license may be found at

-/// http://opensource.org/licenses/bsd-license.php.

-///

-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-///

-/// Module Name:  CpuFlushTlb.s

-///

-///

-

-.auto

-.text

-

-ASM_GLOBAL PalCall

-.type   PalCall, @function

-

-.proc   CpuFlushTlb

-.type   CpuFlushTlb, @function

-CpuFlushTlb::

-        alloc               loc0 = ar.pfs, 0, 3, 5, 0

-        mov                 out0 = 0

-        mov                 out1 = 6

-        mov                 out2 = 0

-        mov                 out3 = 0

-        mov                 loc1 = b0

-        mov                 out4 = 0

-        brl.call.sptk       b0  = PalCall

-        mov                 loc2 = psr              // save PSR

-        mov                 ar.pfs = loc0

-        extr.u              r14 = r10, 32, 32       // r14 <- count1

-        rsm                 1 << 14                 // Disable interrupts

-        extr.u              r15 = r11, 32, 32       // r15 <- stride1

-        extr.u              r10 = r10, 0, 32        // r10 <- count2

-        add                 r10 = -1, r10

-        extr.u              r11 = r11, 0, 32        // r11 <- stride2

-        br.cond.sptk        LoopPredicate

-LoopOuter:

-        mov                 ar.lc = r10             // LC <- count2

-        mov                 ar.ec = r0              // EC <- 0

-Loop:

-        ptc.e               r9

-        add                 r9 = r11, r9            // r9 += stride2

-        br.ctop.sptk        Loop

-        add                 r9 = r15, r9            // r9 += stride1

-LoopPredicate:

-        cmp.ne              p6 = r0, r14            // count1 == 0?

-        add                 r14 = -1, r14

-(p6)    br.cond.sptk        LoopOuter

-        mov                 psr.l = loc2

-        mov                 b0  = loc1

-        br.ret.sptk.many    b0

-.endp

diff --git a/MdePkg/Library/BaseCpuLib/Ipf/CpuSleep.c b/MdePkg/Library/BaseCpuLib/Ipf/CpuSleep.c
deleted file mode 100644
index 59c07cac72..0000000000
--- a/MdePkg/Library/BaseCpuLib/Ipf/CpuSleep.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/** @file

-  Base Library CPU functions for Itanium

-

-  Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>

-  This program and the accompanying materials

-  are licensed and made available under the terms and conditions of the BSD License

-  which accompanies this distribution.  The full text of the license may be found at

-  http://opensource.org/licenses/bsd-license.php.

-

-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-

-**/

-

-#include <Library/PalLib.h>

-#include <Library/BaseLib.h>

-

-/**

-  Places the CPU in a sleep state until an interrupt is received.

-

-  Places the CPU in a sleep state until an interrupt is received. If interrupts

-  are disabled prior to calling this function, then the CPU will be placed in a

-  sleep state indefinitely.

-

-**/

-VOID

-EFIAPI

-CpuSleep (

-  VOID

-  )

-{

-  UINT64  Tpr;

-

-  //

-  // It is the TPR register that controls if external interrupt would bring processor in LIGHT HALT low-power state

-  // back to normal state. PAL_HALT_LIGHT does not depend on PSR setting.

-  // So here if interrupts are disabled (via PSR.i), TRP.mmi needs to be set to prevent processor being interrupted by external interrupts.

-  // If interrupts are enabled, then just use current TRP setting.

-  //

-  if (GetInterruptState ()) {

-    //

-    // If interrupts are enabled, then call PAL_HALT_LIGHT with the current TPR setting.

-    //

-    PalCall (PAL_HALT_LIGHT, 0, 0, 0);

-  } else {

-    //

-    // If interrupts are disabled on entry, then mask all interrupts in TPR before calling PAL_HALT_LIGHT.

-    //

-

-    //

-    // Save TPR

-    //

-    Tpr = AsmReadTpr();

-    //

-    // Set TPR.mmi to mask all external interrupts

-    //

-    AsmWriteTpr (BIT16 | Tpr);

-

-    PalCall (PAL_HALT_LIGHT, 0, 0, 0);

-

-    //

-    // Restore TPR

-    //

-    AsmWriteTpr (Tpr);

-  }

-}