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| author | Jiaxin Wu <jiaxin.wu@intel.com> | 2021-04-01 18:50:53 -0700 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-04-06 00:43:49 +0000 |
| commit | 4ac02962017c77bf38b462f970c884c2dc7931cf (patch) | |
| tree | feef65278a2bffae6c6c6aacc63c7d1599cc911b /MdePkg/Library/BaseLib/BaseLib.inf | |
| parent | f95cdd316c3d56e8f76b5044be54b9645e1dc60f (diff) | |
| download | edk2-4ac02962017c77bf38b462f970c884c2dc7931cf.tar.gz edk2-4ac02962017c77bf38b462f970c884c2dc7931cf.tar.bz2 edk2-4ac02962017c77bf38b462f970c884c2dc7931cf.zip | |
MdePkg/BaseLib: Add support for the XSETBV instruction
*v2: refine the coding format.
https://bugzilla.tianocore.org/show_bug.cgi?id=3284
This patch is to support XSETBV instruction so as to support
Extended Control Register(XCR) write.
Extended Control Register(XCR) read has already been supported
by below commit to support XGETBV instruction:
9b3ca509abd4e45439bbdfe2c2fa8780c950320a
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Ni Ray <ray.ni@intel.com>
Cc: Yao Jiewen <jiewen.yao@intel.com>
Signed-off-by: Jiaxin Wu <Jiaxin.wu@intel.com>
Signed-off-by: Zhang Hongbin1 <hongbin1.zhang@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Diffstat (limited to 'MdePkg/Library/BaseLib/BaseLib.inf')
| -rw-r--r-- | MdePkg/Library/BaseLib/BaseLib.inf | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index 3b85c56c3c..fe8f68bbcf 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -1,7 +1,7 @@ ## @file
# Base Library implementation.
#
-# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
@@ -184,6 +184,7 @@ Ia32/DisableCache.nasm| GCC
Ia32/RdRand.nasm
Ia32/XGetBv.nasm
+ Ia32/XSetBv.nasm
Ia32/VmgExit.nasm
Ia32/DivS64x64Remainder.c
@@ -318,6 +319,7 @@ X64/DisablePaging64.nasm
X64/RdRand.nasm
X64/XGetBv.nasm
+ X64/XSetBv.nasm
X64/VmgExit.nasm
ChkStkGcc.c | GCC
|