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| author | Dandan Bi <dandan.bi@intel.com> | 2021-03-12 18:05:07 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-04-08 02:02:57 +0000 |
| commit | dc4d42302c22f012d78f6495ea23ceaa3e23842e (patch) | |
| tree | dc1137d9d26c25e8a15fa996301da7e64b0c311f /MdePkg/Library/BaseLib/Ia32/ReadMsr64.c | |
| parent | 38c8be123aced4cc8ad5c7e0da9121a181b94251 (diff) | |
| download | edk2-dc4d42302c22f012d78f6495ea23ceaa3e23842e.tar.gz edk2-dc4d42302c22f012d78f6495ea23ceaa3e23842e.tar.bz2 edk2-dc4d42302c22f012d78f6495ea23ceaa3e23842e.zip | |
MdePkg/Baseib: Filter/trace MSR access for IA32/X64
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3246
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Diffstat (limited to 'MdePkg/Library/BaseLib/Ia32/ReadMsr64.c')
| -rw-r--r-- | MdePkg/Library/BaseLib/Ia32/ReadMsr64.c | 38 |
1 files changed, 34 insertions, 4 deletions
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c b/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c index 6d2394b1a3..afe3aa5bdc 100644 --- a/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c +++ b/MdePkg/Library/BaseLib/Ia32/ReadMsr64.c @@ -1,13 +1,13 @@ /** @file
AsmReadMsr64 function
- Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
-
+#include <Library/RegisterFilterLib.h>
/**
Returns a 64-bit Machine Specific Register(MSR).
@@ -24,8 +24,7 @@ **/
UINT64
-EFIAPI
-AsmReadMsr64 (
+AsmReadMsr64Internal (
IN UINT32 Index
)
{
@@ -35,3 +34,34 @@ AsmReadMsr64 ( }
}
+/**
+ Returns a 64-bit Machine Specific Register(MSR).
+
+ Reads and returns the 64-bit MSR specified by Index. No parameter checking is
+ performed on Index, and some Index values may cause CPU exceptions. The
+ caller must either guarantee that Index is valid, or the caller must set up
+ exception handlers to catch the exceptions. This function is only available
+ on IA-32 and x64.
+
+ @param Index The 32-bit MSR index to read.
+
+ @return The value of the MSR identified by Index.
+
+**/
+UINT64
+EFIAPI
+AsmReadMsr64 (
+ IN UINT32 Index
+ )
+{
+ UINT64 Value;
+ BOOLEAN Flag;
+
+ Flag = FilterBeforeMsrRead (Index, &Value);
+ if (Flag) {
+ Value = AsmReadMsr64Internal (Index);
+ }
+ FilterAfterMsrRead (Index, &Value);
+
+ return Value;
+}
|