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authorxli24 <xli24@6f19259b-4bc3-4df7-8a09-765794883524>2009-05-14 03:13:31 +0000
committerxli24 <xli24@6f19259b-4bc3-4df7-8a09-765794883524>2009-05-14 03:13:31 +0000
commit59ceeabe504f4c7814f9560c411690a1ffdc31b2 (patch)
tree07838aa3ccbe32341dffa18d8b2f5ecc50ecbda0 /MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c
parentc40a1556902e65bf4e998fad0c9a34684e84da10 (diff)
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1. Add address check for "RegisterForRuntime" APIs of PciLib, PciCf8Lib, PciExpressLib, and PciSegmentLib.
2. Update ASSERT condition for PciCf8Lib, and PciSegmentLib class. 3. According to MDE Lib Spec, add check for reserved bit field 63..48 for PCI segment address. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8311 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c')
-rw-r--r--MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c11
1 files changed, 6 insertions, 5 deletions
diff --git a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c
index beb8b64adf..97fd240a0e 100644
--- a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c
+++ b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c
@@ -1,7 +1,7 @@
/** @file
PCI Segment Library implementation using PCI Root Bridge I/O Protocol.
- Copyright (c) 2007 - 2008, Intel Corporation All rights
+ Copyright (c) 2007 - 2009, Intel Corporation All rights
reserved. This program and the accompanying materials are
licensed and made available under the terms and conditions of
the BSD License which accompanies this distribution. The full
@@ -244,7 +244,7 @@ DxePciSegmentLibPciRootBridgeIoWriteWorker (
Register a PCI device so PCI configuration registers may be accessed after
SetVirtualAddressMap().
- If Address > 0x0FFFFFFF, then ASSERT().
+ If any reserved bits in Address are set, then ASSERT().
@param Address Address that encodes the PCI Bus, Device, Function and
Register.
@@ -264,6 +264,7 @@ PciSegmentRegisterForRuntimeAccess (
IN UINTN Address
)
{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
return RETURN_UNSUPPORTED;
}
@@ -297,7 +298,7 @@ PciSegmentRead8 (
Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
Value is returned. This function must guarantee that all PCI read and write operations are serialized.
- If Address > 0x0FFFFFFF, then ASSERT().
+ If any reserved bits in Address are set, then ASSERT().
@param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@param Value The value to write.
@@ -1287,7 +1288,7 @@ PciSegmentBitFieldAndThenOr32 (
and 16-bit PCI configuration read cycles may be used at the beginning and the
end of the range.
- If StartAddress > 0x0FFFFFFF, then ASSERT().
+ If any reserved bits in StartAddress are set, then ASSERT().
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
If Size > 0 and Buffer is NULL, then ASSERT().
@@ -1385,7 +1386,7 @@ PciSegmentReadBuffer (
8-bit and 16-bit PCI configuration write cycles may be used at the beginning
and the end of the range.
- If StartAddress > 0x0FFFFFFF, then ASSERT().
+ If any reserved bits in StartAddress are set, then ASSERT().
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
If Size > 0 and Buffer is NULL, then ASSERT().