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| author | Abner Chang <abner.chang@hpe.com> | 2020-04-07 15:59:20 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-05-07 03:17:15 +0000 |
| commit | 3fd8800954b589cf69e31686f8a6ba6bf200ca3f (patch) | |
| tree | c70ddaf79b71e591cd396408fcbe4ff872bdb141 /MdePkg/Library | |
| parent | 54a3d5ec48e05ae5e5b003d69b1ea55bc09188a9 (diff) | |
| download | edk2-3fd8800954b589cf69e31686f8a6ba6bf200ca3f.tar.gz edk2-3fd8800954b589cf69e31686f8a6ba6bf200ca3f.tar.bz2 edk2-3fd8800954b589cf69e31686f8a6ba6bf200ca3f.zip | |
MdePkg/BaseCpuLib: RISC-V Base CPU library
implementation.
Implement RISC-V CPU related functions in BaseCpuLib.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
Diffstat (limited to 'MdePkg/Library')
| -rw-r--r-- | MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 6 | ||||
| -rw-r--r-- | MdePkg/Library/BaseCpuLib/BaseCpuLib.uni | 5 | ||||
| -rw-r--r-- | MdePkg/Library/BaseCpuLib/RiscV/Cpu.S | 19 |
3 files changed, 27 insertions, 3 deletions
diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf index a7cb381a85..950f5229b2 100644 --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf @@ -7,6 +7,7 @@ # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -24,7 +25,7 @@ #
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
#
[Sources.IA32]
@@ -59,6 +60,9 @@ AArch64/CpuFlushTlb.asm | MSFT
AArch64/CpuSleep.asm | MSFT
+[Sources.RISCV64]
+ RiscV/Cpu.S
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni index fc95cda9fc..80dc495786 100644 --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni @@ -1,12 +1,13 @@ // /** @file
// Instance of CPU Library for various architecture.
//
-// CPU Library implemented using ASM functions for IA-32 and X64,
+// CPU Library implemented using ASM functions for IA-32, X64 and RISCV64,
// PAL CALLs for IPF, and empty functions for EBC.
//
// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
// Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -15,5 +16,5 @@ #string STR_MODULE_ABSTRACT #language en-US "Instance of CPU Library for various architectures"
-#string STR_MODULE_DESCRIPTION #language en-US "CPU Library implemented using ASM functions for IA-32 and X64, PAL CALLs for IPF, and empty functions for EBC."
+#string STR_MODULE_DESCRIPTION #language en-US "CPU Library implemented using ASM functions for IA-32, X64 and RISCV64, PAL CALLs for IPF, and empty functions for EBC."
diff --git a/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S b/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S new file mode 100644 index 0000000000..375b91d314 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S @@ -0,0 +1,19 @@ +//------------------------------------------------------------------------------
+//
+// CpuSleep for RISC-V
+//
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+.data
+.align 3
+.section .text
+
+.global ASM_PFX(_CpuSleep)
+
+ASM_PFX(_CpuSleep):
+ wfi
+ ret
+
+
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