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| author | Oliver Smith-Denny <osde@linux.microsoft.com> | 2024-08-05 10:25:07 -0700 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2024-09-12 19:36:59 +0000 |
| commit | 8f74b95a21cf106fa4eb4932e22b404c57297ba2 (patch) | |
| tree | 378f21f82997945b07d8149d79f12cf059342aa8 /MdePkg | |
| parent | 734e71f428a4fdac5d82ae9c093911053356f6ff (diff) | |
| download | edk2-8f74b95a21cf106fa4eb4932e22b404c57297ba2.tar.gz edk2-8f74b95a21cf106fa4eb4932e22b404c57297ba2.tar.bz2 edk2-8f74b95a21cf106fa4eb4932e22b404c57297ba2.zip | |
MdePkg: Move CompilerIntrinsicsLib from ArmPkg
As per the emailed RFC in
https://edk2.groups.io/g/devel/topic/rfc_move/107675828,
this patch moves CompilerIntrinsicsLib from ArmPkg to
MdePkg as this library provides compiler intrinsics, which
are industry standard.
This aligns with the goal of integrating ArmPkg into existing
packages: https://bugzilla.tianocore.org/show_bug.cgi?id=4121.
The newly placed CompilerIntrinsicsLib is added to MdeLibs.dsc.inc
as every DSC that builds ARM/AARCH64 needs this library added. The
old location is removed from every DSC in edk2 in this commit also
to not break bisectability with minimal hoop jumping.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
Diffstat (limited to 'MdePkg')
46 files changed, 2773 insertions, 0 deletions
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/AArch64/Atomics.S b/MdePkg/Library/CompilerIntrinsicsLib/AArch64/Atomics.S new file mode 100644 index 0000000000..3792020ab8 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/AArch64/Atomics.S @@ -0,0 +1,142 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2020, Arm, Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+ /*
+ * Provide the GCC intrinsics that are required when using GCC 9 or
+ * later with the -moutline-atomics options (which became the default
+ * in GCC 10)
+ */
+ .arch armv8-a
+
+ .macro reg_alias, pfx, sz
+ r0_\sz .req \pfx\()0
+ r1_\sz .req \pfx\()1
+ tmp0_\sz .req \pfx\()16
+ tmp1_\sz .req \pfx\()17
+ .endm
+
+ /*
+ * Define register aliases of the right type for each size
+ * (xN for 8 bytes, wN for everything smaller)
+ */
+ reg_alias w, 1
+ reg_alias w, 2
+ reg_alias w, 4
+ reg_alias x, 8
+
+ .macro fn_start, name:req
+ .section .text.\name
+ .globl \name
+ .type \name, %function
+\name\():
+ .endm
+
+ .macro fn_end, name:req
+ .size \name, . - \name
+ .endm
+
+ /*
+ * Emit an atomic helper for \model with operands of size \sz, using
+ * the operation specified by \insn (which is the LSE name), and which
+ * can be implemented using the generic load-locked/store-conditional
+ * (LL/SC) sequence below, using the arithmetic operation given by
+ * \opc.
+ */
+ .macro emit_ld_sz, sz:req, insn:req, opc:req, model:req, s, a, l
+ fn_start __aarch64_\insn\()\sz\()\model
+ mov tmp0_\sz, r0_\sz
+0: ld\a\()xr\s r0_\sz, [x1]
+ .ifnc \insn, swp
+ \opc tmp1_\sz, r0_\sz, tmp0_\sz
+ st\l\()xr\s w15, tmp1_\sz, [x1]
+ .else
+ st\l\()xr\s w15, tmp0_\sz, [x1]
+ .endif
+ cbnz w15, 0b
+ ret
+ fn_end __aarch64_\insn\()\sz\()\model
+ .endm
+
+ /*
+ * Emit atomic helpers for \model for operand sizes in the
+ * set {1, 2, 4, 8}, for the instruction pattern given by
+ * \insn. (This is the LSE name, but this implementation uses
+ * the generic LL/SC sequence using \opc as the arithmetic
+ * operation on the target.)
+ */
+ .macro emit_ld, insn:req, opc:req, model:req, a, l
+ emit_ld_sz 1, \insn, \opc, \model, b, \a, \l
+ emit_ld_sz 2, \insn, \opc, \model, h, \a, \l
+ emit_ld_sz 4, \insn, \opc, \model, , \a, \l
+ emit_ld_sz 8, \insn, \opc, \model, , \a, \l
+ .endm
+
+ /*
+ * Emit the compare and swap helper for \model and size \sz
+ * using LL/SC instructions.
+ */
+ .macro emit_cas_sz, sz:req, model:req, uxt:req, s, a, l
+ fn_start __aarch64_cas\sz\()\model
+ \uxt tmp0_\sz, r0_\sz
+0: ld\a\()xr\s r0_\sz, [x2]
+ cmp r0_\sz, tmp0_\sz
+ bne 1f
+ st\l\()xr\s w15, r1_\sz, [x2]
+ cbnz w15, 0b
+1: ret
+ fn_end __aarch64_cas\sz\()\model
+ .endm
+
+ /*
+ * Emit compare-and-swap helpers for \model for operand sizes in the
+ * set {1, 2, 4, 8, 16}.
+ */
+ .macro emit_cas, model:req, a, l
+ emit_cas_sz 1, \model, uxtb, b, \a, \l
+ emit_cas_sz 2, \model, uxth, h, \a, \l
+ emit_cas_sz 4, \model, mov , , \a, \l
+ emit_cas_sz 8, \model, mov , , \a, \l
+
+ /*
+ * We cannot use the parameterized sequence for 16 byte CAS, so we
+ * need to define it explicitly.
+ */
+ fn_start __aarch64_cas16\model
+ mov x16, x0
+ mov x17, x1
+0: ld\a\()xp x0, x1, [x4]
+ cmp x0, x16
+ ccmp x1, x17, #0, eq
+ bne 1f
+ st\l\()xp w15, x16, x17, [x4]
+ cbnz w15, 0b
+1: ret
+ fn_end __aarch64_cas16\model
+ .endm
+
+ /*
+ * Emit the set of GCC outline atomic helper functions for
+ * the memory ordering model given by \model:
+ * - relax unordered loads and stores
+ * - acq load-acquire, unordered store
+ * - rel unordered load, store-release
+ * - acq_rel load-acquire, store-release
+ */
+ .macro emit_model, model:req, a, l
+ emit_ld ldadd, add, \model, \a, \l
+ emit_ld ldclr, bic, \model, \a, \l
+ emit_ld ldeor, eor, \model, \a, \l
+ emit_ld ldset, orr, \model, \a, \l
+ emit_ld swp, mov, \model, \a, \l
+ emit_cas \model, \a, \l
+ .endm
+
+ emit_model _relax
+ emit_model _acq, a
+ emit_model _rel,, l
+ emit_model _acq_rel, a, l
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/AArch64/ashlti3.S b/MdePkg/Library/CompilerIntrinsicsLib/AArch64/ashlti3.S new file mode 100644 index 0000000000..77348a0cff --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/AArch64/ashlti3.S @@ -0,0 +1,33 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+ASM_FUNC(__ashlti3)
+ # return if shift is 0
+ cbz x2, 1f
+
+ mov x3, #64
+ sub x3, x3, x2
+ cmp x3, #0
+ b.le 2f
+
+ # shift is <= 64 bits
+ lsr x3, x0, x3
+ lsl x1, x1, x2
+ orr x1, x1, x3
+ lsl x0, x0, x2
+1:
+ ret
+
+2:
+ # shift is > 64
+ neg w3, w3
+ lsl x1, x0, x3
+ mov x0, #0
+ ret
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.S new file mode 100644 index 0000000000..f5f14509c5 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.S @@ -0,0 +1,27 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+ASM_FUNC(__ashldi3)
+ cmp r2, #31
+ bls L2
+ cmp r2, #63
+ subls r2, r2, #32
+ movls r2, r0, asl r2
+ movhi r2, #0
+ mov r1, r2
+ mov r0, #0
+ bx lr
+L2:
+ cmp r2, #0
+ rsbne r3, r2, #32
+ movne r3, r0, lsr r3
+ movne r0, r0, asl r2
+ orrne r1, r3, r1, asl r2
+ bx lr
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.S new file mode 100644 index 0000000000..855497e7d1 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.S @@ -0,0 +1,28 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+ASM_FUNC(__ashrdi3)
+ cmp r2, #31
+ bls L2
+ cmp r2, #63
+ subls r2, r2, #32
+ mov ip, r1, asr #31
+ movls r2, r1, asr r2
+ movhi r2, ip
+ mov r0, r2
+ mov r1, ip
+ bx lr
+L2:
+ cmp r2, #0
+ rsbne r3, r2, #32
+ movne r3, r1, asl r3
+ movne r1, r1, asr r2
+ orrne r0, r3, r0, lsr r2
+ bx lr
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/clzsi2.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/clzsi2.S new file mode 100644 index 0000000000..54a7f3cd83 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/clzsi2.S @@ -0,0 +1,49 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+ASM_FUNC(__clzsi2)
+ @ frame_needed = 1, uses_anonymous_args = 0
+ stmfd sp!, {r7, lr}
+ add r7, sp, #0
+ movs r3, r0, lsr #16
+ movne r3, #16
+ moveq r3, #0
+ movne r9, #0
+ moveq r9, #16
+ mov r3, r0, lsr r3
+ tst r3, #65280
+ movne r0, #8
+ moveq r0, #0
+ movne lr, #0
+ moveq lr, #8
+ mov r3, r3, lsr r0
+ tst r3, #240
+ movne r0, #4
+ moveq r0, #0
+ movne ip, #0
+ moveq ip, #4
+ mov r3, r3, lsr r0
+ tst r3, #12
+ movne r0, #2
+ moveq r0, #0
+ movne r1, #0
+ moveq r1, #2
+ mov r2, r3, lsr r0
+ add r3, lr, r9
+ add r0, r3, ip
+ add r1, r0, r1
+ mov r0, r2, lsr #1
+ eor r0, r0, #1
+ ands r0, r0, #1
+ mvnne r0, #0
+ rsb r3, r2, #2
+ and r0, r0, r3
+ add r0, r1, r0
+ ldmfd sp!, {r7, pc}
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/ctzsi2.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/ctzsi2.S new file mode 100644 index 0000000000..d1ff500d5d --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/ctzsi2.S @@ -0,0 +1,41 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+ASM_FUNC(__ctzsi2)
+ uxth r3, r0
+ cmp r3, #0
+ moveq ip, #16
+ movne ip, #0
+ @ lr needed for prologue
+ mov r0, r0, lsr ip
+ tst r0, #255
+ movne r3, #0
+ moveq r3, #8
+ mov r0, r0, lsr r3
+ tst r0, #15
+ movne r1, #0
+ moveq r1, #4
+ add r3, r3, ip
+ mov r0, r0, lsr r1
+ tst r0, #3
+ movne r2, #0
+ moveq r2, #2
+ add r3, r3, r1
+ mov r0, r0, lsr r2
+ and r0, r0, #3
+ add r2, r3, r2
+ eor r3, r0, #1
+ mov r0, r0, lsr #1
+ ands r3, r3, #1
+ mvnne r3, #0
+ rsb r0, r0, #2
+ and r0, r3, r0
+ add r0, r2, r0
+ bx lr
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/div.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/div.S new file mode 100644 index 0000000000..d6075ab33a --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/div.S @@ -0,0 +1,147 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2011, ARM. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.align 2
+GCC_ASM_EXPORT(__aeabi_uidiv)
+GCC_ASM_EXPORT(__aeabi_uidivmod)
+GCC_ASM_EXPORT(__aeabi_idiv)
+GCC_ASM_EXPORT(__aeabi_idivmod)
+
+# AREA Math, CODE, READONLY
+
+#
+#UINT32
+#EFIAPI
+#__aeabi_uidivmode (
+# IN UINT32 Dividen
+# IN UINT32 Divisor
+# );
+#
+
+ASM_PFX(__aeabi_uidiv):
+ASM_PFX(__aeabi_uidivmod):
+ rsbs r12, r1, r0, LSR #4
+ mov r2, #0
+ bcc ASM_PFX(__arm_div4)
+ rsbs r12, r1, r0, LSR #8
+ bcc ASM_PFX(__arm_div8)
+ mov r3, #0
+ b ASM_PFX(__arm_div_large)
+
+#
+#INT32
+#EFIAPI
+#__aeabi_idivmode (
+# IN INT32 Dividen
+# IN INT32 Divisor
+# );
+#
+ASM_PFX(__aeabi_idiv):
+ASM_PFX(__aeabi_idivmod):
+ orrs r12, r0, r1
+ bmi ASM_PFX(__arm_div_negative)
+ rsbs r12, r1, r0, LSR #1
+ mov r2, #0
+ bcc ASM_PFX(__arm_div1)
+ rsbs r12, r1, r0, LSR #4
+ bcc ASM_PFX(__arm_div4)
+ rsbs r12, r1, r0, LSR #8
+ bcc ASM_PFX(__arm_div8)
+ mov r3, #0
+ b ASM_PFX(__arm_div_large)
+ASM_PFX(__arm_div8):
+ rsbs r12, r1, r0, LSR #7
+ subcs r0, r0, r1, LSL #7
+ adc r2, r2, r2
+ rsbs r12, r1, r0,LSR #6
+ subcs r0, r0, r1, LSL #6
+ adc r2, r2, r2
+ rsbs r12, r1, r0, LSR #5
+ subcs r0, r0, r1, LSL #5
+ adc r2, r2, r2
+ rsbs r12, r1, r0, LSR #4
+ subcs r0, r0, r1, LSL #4
+ adc r2, r2, r2
+ASM_PFX(__arm_div4):
+ rsbs r12, r1, r0, LSR #3
+ subcs r0, r0, r1, LSL #3
+ adc r2, r2, r2
+ rsbs r12, r1, r0, LSR #2
+ subcs r0, r0, r1, LSL #2
+ adcs r2, r2, r2
+ rsbs r12, r1, r0, LSR #1
+ subcs r0, r0, r1, LSL #1
+ adc r2, r2, r2
+ASM_PFX(__arm_div1):
+ subs r1, r0, r1
+ movcc r1, r0
+ adc r0, r2, r2
+ bx r14
+ASM_PFX(__arm_div_negative):
+ ands r2, r1, #0x80000000
+ rsbmi r1, r1, #0
+ eors r3, r2, r0, ASR #32
+ rsbcs r0, r0, #0
+ rsbs r12, r1, r0, LSR #4
+ bcc label1
+ rsbs r12, r1, r0, LSR #8
+ bcc label2
+ASM_PFX(__arm_div_large):
+ lsl r1, r1, #6
+ rsbs r12, r1, r0, LSR #8
+ orr r2, r2, #0xfc000000
+ bcc label2
+ lsl r1, r1, #6
+ rsbs r12, r1, r0, LSR #8
+ orr r2, r2, #0x3f00000
+ bcc label2
+ lsl r1, r1, #6
+ rsbs r12, r1, r0, LSR #8
+ orr r2, r2, #0xfc000
+ orrcs r2, r2, #0x3f00
+ lslcs r1, r1, #6
+ rsbs r12, r1, #0
+ bcs ASM_PFX(__aeabi_idiv0)
+label3:
+ lsrcs r1, r1, #6
+label2:
+ rsbs r12, r1, r0, LSR #7
+ subcs r0, r0, r1, LSL #7
+ adc r2, r2, r2
+ rsbs r12, r1, r0, LSR #6
+ subcs r0, r0, r1, LSL #6
+ adc r2, r2, r2
+ rsbs r12, r1, r0, LSR #5
+ subcs r0, r0, r1, LSL #5
+ adc r2, r2, r2
+ rsbs r12, r1, r0, LSR #4
+ subcs r0, r0, r1, LSL #4
+ adc r2, r2, r2
+label1:
+ rsbs r12, r1, r0, LSR #3
+ subcs r0, r0, r1, LSL #3
+ adc r2, r2, r2
+ rsbs r12, r1, r0, LSR #2
+ subcs r0, r0, r1, LSL #2
+ adcs r2, r2, r2
+ bcs label3
+ rsbs r12, r1, r0, LSR #1
+ subcs r0, r0, r1, LSL #1
+ adc r2, r2, r2
+ subs r1, r0, r1
+ movcc r1, r0
+ adc r0, r2, r2
+ asrs r3, r3, #31
+ rsbmi r0, r0, #0
+ rsbcs r1, r1, #0
+ bx r14
+
+ @ What to do about division by zero? For now, just return.
+ASM_PFX(__aeabi_idiv0):
+ bx r14
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/div.asm b/MdePkg/Library/CompilerIntrinsicsLib/Arm/div.asm new file mode 100644 index 0000000000..3cbeaa4c1b --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/div.asm @@ -0,0 +1,180 @@ +//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+// Copyright (c) 2018, Pete Batard. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+
+ EXPORT __aeabi_uidiv
+ EXPORT __aeabi_uidivmod
+ EXPORT __aeabi_idiv
+ EXPORT __aeabi_idivmod
+ EXPORT __rt_udiv
+ EXPORT __rt_sdiv
+
+ AREA Math, CODE, READONLY
+
+;
+;UINT32
+;EFIAPI
+;__aeabi_uidivmod (
+; IN UINT32 Dividend
+; IN UINT32 Divisor
+; );
+;
+__aeabi_uidiv
+__aeabi_uidivmod
+ RSBS r12, r1, r0, LSR #4
+ MOV r2, #0
+ BCC __arm_div4
+ RSBS r12, r1, r0, LSR #8
+ BCC __arm_div8
+ MOV r3, #0
+ B __arm_div_large
+
+;
+;UINT64
+;EFIAPI
+;__rt_udiv (
+; IN UINT32 Divisor,
+; IN UINT32 Dividend
+; );
+;
+__rt_udiv
+ ; Swap R0 and R1
+ MOV r12, r0
+ MOV r0, r1
+ MOV r1, r12
+ B __aeabi_uidivmod
+
+;
+;UINT64
+;EFIAPI
+;__rt_sdiv (
+; IN INT32 Divisor,
+; IN INT32 Dividend
+; );
+;
+__rt_sdiv
+ ; Swap R0 and R1
+ MOV r12, r0
+ MOV r0, r1
+ MOV r1, r12
+ B __aeabi_idivmod
+
+;
+;INT32
+;EFIAPI
+;__aeabi_idivmod (
+; IN INT32 Dividend
+; IN INT32 Divisor
+; );
+;
+__aeabi_idiv
+__aeabi_idivmod
+ ORRS r12, r0, r1
+ BMI __arm_div_negative
+ RSBS r12, r1, r0, LSR #1
+ MOV r2, #0
+ BCC __arm_div1
+ RSBS r12, r1, r0, LSR #4
+ BCC __arm_div4
+ RSBS r12, r1, r0, LSR #8
+ BCC __arm_div8
+ MOV r3, #0
+ B __arm_div_large
+__arm_div8
+ RSBS r12, r1, r0, LSR #7
+ SUBCS r0, r0, r1, LSL #7
+ ADC r2, r2, r2
+ RSBS r12, r1, r0,LSR #6
+ SUBCS r0, r0, r1, LSL #6
+ ADC r2, r2, r2
+ RSBS r12, r1, r0, LSR #5
+ SUBCS r0, r0, r1, LSL #5
+ ADC r2, r2, r2
+ RSBS r12, r1, r0, LSR #4
+ SUBCS r0, r0, r1, LSL #4
+ ADC r2, r2, r2
+__arm_div4
+ RSBS r12, r1, r0, LSR #3
+ SUBCS r0, r0, r1, LSL #3
+ ADC r2, r2, r2
+ RSBS r12, r1, r0, LSR #2
+ SUBCS r0, r0, r1, LSL #2
+ ADCS r2, r2, r2
+ RSBS r12, r1, r0, LSR #1
+ SUBCS r0, r0, r1, LSL #1
+ ADC r2, r2, r2
+__arm_div1
+ SUBS r1, r0, r1
+ MOVCC r1, r0
+ ADC r0, r2, r2
+ BX r14
+__arm_div_negative
+ ANDS r2, r1, #0x80000000
+ RSBMI r1, r1, #0
+ EORS r3, r2, r0, ASR #32
+ RSBCS r0, r0, #0
+ RSBS r12, r1, r0, LSR #4
+ BCC label1
+ RSBS r12, r1, r0, LSR #8
+ BCC label2
+__arm_div_large
+ LSL r1, r1, #6
+ RSBS r12, r1, r0, LSR #8
+ ORR r2, r2, #0xfc000000
+ BCC label2
+ LSL r1, r1, #6
+ RSBS r12, r1, r0, LSR #8
+ ORR r2, r2, #0x3f00000
+ BCC label2
+ LSL r1, r1, #6
+ RSBS r12, r1, r0, LSR #8
+ ORR r2, r2, #0xfc000
+ ORRCS r2, r2, #0x3f00
+ LSLCS r1, r1, #6
+ RSBS r12, r1, #0
+ BCS __aeabi_idiv0
+label3
+ LSRCS r1, r1, #6
+label2
+ RSBS r12, r1, r0, LSR #7
+ SUBCS r0, r0, r1, LSL #7
+ ADC r2, r2, r2
+ RSBS r12, r1, r0, LSR #6
+ SUBCS r0, r0, r1, LSL #6
+ ADC r2, r2, r2
+ RSBS r12, r1, r0, LSR #5
+ SUBCS r0, r0, r1, LSL #5
+ ADC r2, r2, r2
+ RSBS r12, r1, r0, LSR #4
+ SUBCS r0, r0, r1, LSL #4
+ ADC r2, r2, r2
+label1
+ RSBS r12, r1, r0, LSR #3
+ SUBCS r0, r0, r1, LSL #3
+ ADC r2, r2, r2
+ RSBS r12, r1, r0, LSR #2
+ SUBCS r0, r0, r1, LSL #2
+ ADCS r2, r2, r2
+ BCS label3
+ RSBS r12, r1, r0, LSR #1
+ SUBCS r0, r0, r1, LSL #1
+ ADC r2, r2, r2
+ SUBS r1, r0, r1
+ MOVCC r1, r0
+ ADC r0, r2, r2
+ ASRS r3, r3, #31
+ RSBMI r0, r0, #0
+ RSBCS r1, r1, #0
+ BX r14
+
+ ; What to do about division by zero? For now, just return.
+__aeabi_idiv0
+ BX r14
+
+ END
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/divdi3.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/divdi3.S new file mode 100644 index 0000000000..c1c3c77b25 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/divdi3.S @@ -0,0 +1,41 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+ASM_FUNC(__divdi3)
+ @ args = 0, pretend = 0, frame = 0
+ @ frame_needed = 1, uses_anonymous_args = 0
+ stmfd sp!, {r4, r5, r7, lr}
+ mov r4, r3, asr #31
+ add r7, sp, #8
+ stmfd sp!, {r10, r11}
+ mov r10, r1, asr #31
+ sub sp, sp, #8
+ mov r11, r10
+ mov r5, r4
+ eor r0, r0, r10
+ eor r1, r1, r10
+ eor r2, r2, r4
+ eor r3, r3, r4
+ subs r2, r2, r4
+ sbc r3, r3, r5
+ mov ip, #0
+ subs r0, r0, r10
+ sbc r1, r1, r11
+ str ip, [sp, #0]
+ bl ASM_PFX(__udivmoddi4)
+ eor r2, r10, r4
+ eor r3, r10, r4
+ eor r0, r0, r2
+ eor r1, r1, r3
+ subs r0, r0, r2
+ sbc r1, r1, r3
+ sub sp, r7, #16
+ ldmfd sp!, {r10, r11}
+ ldmfd sp!, {r4, r5, r7, pc}
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/divsi3.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/divsi3.S new file mode 100644 index 0000000000..eb4c30f6a2 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/divsi3.S @@ -0,0 +1,24 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+ASM_FUNC(__divsi3)
+ eor r3, r0, r0, asr #31
+ eor r2, r1, r1, asr #31
+ stmfd sp!, {r4, r5, r7, lr}
+ mov r5, r0, asr #31
+ add r7, sp, #8
+ mov r4, r1, asr #31
+ sub r0, r3, r0, asr #31
+ sub r1, r2, r1, asr #31
+ bl ASM_PFX(__udivsi3)
+ eor r1, r5, r4
+ eor r0, r0, r1
+ rsb r0, r1, r0
+ ldmfd sp!, {r4, r5, r7, pc}
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/lasr.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/lasr.S new file mode 100644 index 0000000000..27201de4be --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/lasr.S @@ -0,0 +1,30 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+#
+#UINT64
+#EFIAPI
+#__aeabi_lasr (
+# IN UINT64 Value
+# IN UINT32 Shift
+# );
+#
+ASM_FUNC(__aeabi_lasr)
+ subs r3,r2,#0x20
+ bpl L_Test
+ rsb r3,r2,#0x20
+ lsr r0,r0,r2
+ orr r0,r0,r1,LSL r3
+ asr r1,r1,r2
+ bx lr
+L_Test:
+ asr r0,r1,r3
+ asr r1,r1,#31
+ bx lr
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.S new file mode 100644 index 0000000000..15c99c5099 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.S @@ -0,0 +1,50 @@ +//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+//
+// A pair of (unsigned) long longs is returned in {{r0, r1}, {r2, r3}},
+// the quotient in {r0, r1}, and the remainder in {r2, r3}.
+//
+//__value_in_regs lldiv_t
+//EFIAPI
+//__aeabi_ldivmod (
+// IN UINT64 Dividen
+// IN UINT64 Divisor
+// )//
+//
+
+ASM_FUNC(__aeabi_ldivmod)
+ push {r4,lr}
+ asrs r4,r1,#1
+ eor r4,r4,r3,LSR #1
+ bpl L_Test1
+ rsbs r0,r0,#0
+ rsc r1,r1,#0
+L_Test1:
+ tst r3,r3
+ bpl L_Test2
+ rsbs r2,r2,#0
+ rsc r3,r3,#0
+L_Test2:
+ bl ASM_PFX(__aeabi_uldivmod)
+ tst r4,#0x40000000
+ beq L_Test3
+ rsbs r0,r0,#0
+ rsc r1,r1,#0
+L_Test3:
+ tst r4,#0x80000000
+ beq L_Exit
+ rsbs r2,r2,#0
+ rsc r3,r3,#0
+L_Exit:
+ pop {r4,pc}
+
+
+
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.asm b/MdePkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.asm new file mode 100644 index 0000000000..310b2e70db --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.asm @@ -0,0 +1,71 @@ +//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+// Copyright (c) 2018, Pete Batard. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+
+ IMPORT __aeabi_uldivmod
+ EXPORT __aeabi_ldivmod
+ EXPORT __rt_sdiv64
+
+ AREA s___aeabi_ldivmod, CODE, READONLY, ARM
+
+ ARM
+
+;
+;INT64
+;EFIAPI
+;__rt_sdiv64 (
+; IN INT64 Divisor
+; IN INT64 Dividend
+; );
+;
+__rt_sdiv64
+ ; Swap r0-r1 and r2-r3
+ MOV r12, r0
+ MOV r0, r2
+ MOV r2, r12
+ MOV r12, r1
+ MOV r1, r3
+ MOV r3, r12
+ B __aeabi_ldivmod
+
+;
+;INT64
+;EFIAPI
+;__aeabi_ldivmod (
+; IN INT64 Dividend
+; IN INT64 Divisor
+; );
+;
+__aeabi_ldivmod
+ PUSH {r4,lr}
+ ASRS r4,r1,#1
+ EOR r4,r4,r3,LSR #1
+ BPL L_Test1
+ RSBS r0,r0,#0
+ RSC r1,r1,#0
+L_Test1
+ TST r3,r3
+ BPL L_Test2
+ RSBS r2,r2,#0
+ RSC r3,r3,#0
+L_Test2
+ BL __aeabi_uldivmod
+ TST r4,#0x40000000
+ BEQ L_Test3
+ RSBS r0,r0,#0
+ RSC r1,r1,#0
+L_Test3
+ TST r4,#0x80000000
+ BEQ L_Exit
+ RSBS r2,r2,#0
+ RSC r3,r3,#0
+L_Exit
+ POP {r4,pc}
+
+ END
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/llsl.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/llsl.S new file mode 100644 index 0000000000..d0a4acd8bd --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/llsl.S @@ -0,0 +1,31 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2013, ARM. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+#
+#VOID
+#EFIAPI
+#__aeabi_llsl (
+# IN VOID *Destination,
+# IN VOID *Source,
+# IN UINT32 Size
+# );
+#
+ASM_FUNC(__aeabi_llsl)
+ subs r3,r2,#0x20
+ bpl 1f
+ rsb r3,r2,#0x20
+ lsl r1,r1,r2
+ orr r1,r1,r0,lsr r3
+ lsl r0,r0,r2
+ bx lr
+1:
+ lsl r1,r0,r3
+ mov r0,#0
+ bx lr
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/llsr.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/llsr.S new file mode 100644 index 0000000000..af6fd27028 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/llsr.S @@ -0,0 +1,30 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2013, ARM. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+#VOID
+#EFIAPI
+#__aeabi_llsr (
+# IN VOID *Destination,
+# IN VOID *Source,
+# IN UINT32 Size
+# );
+#
+ASM_FUNC(__aeabi_llsr)
+ subs r3,r2,#0x20
+ bpl 1f
+ rsb r3,r2,#0x20
+ lsr r0,r0,r2
+ orr r0,r0,r1,lsl r3
+ lsr r1,r1,r2
+ bx lr
+1:
+ lsr r0,r1,r3
+ mov r1,#0
+ bx lr
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/llsr.asm b/MdePkg/Library/CompilerIntrinsicsLib/Arm/llsr.asm new file mode 100644 index 0000000000..fce1df28f0 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/llsr.asm @@ -0,0 +1,39 @@ +//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+// Copyright (c) 2018, Pete Batard. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+ EXPORT __aeabi_llsr
+ EXPORT __rt_srsh
+
+ AREA s___aeabi_llsr, CODE, READONLY, ARM
+
+ ARM
+
+;
+;VOID
+;EFIAPI
+;__aeabi_llsr (
+; IN UINT64 Value,
+; IN UINT32 Shift
+;)
+;
+__aeabi_llsr
+__rt_srsh
+ SUBS r3,r2,#0x20
+ BPL __aeabi_llsr_label1
+ RSB r3,r2,#0x20
+ LSR r0,r0,r2
+ ORR r0,r0,r1,LSL r3
+ LSR r1,r1,r2
+ BX lr
+__aeabi_llsr_label1
+ LSR r0,r1,r3
+ MOV r1,#0
+ BX lr
+
+ END
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.S new file mode 100644 index 0000000000..288573c855 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.S @@ -0,0 +1,27 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+ASM_FUNC(__lshrdi3)
+ cmp r2, #31
+ bls L2
+ cmp r2, #63
+ subls r2, r2, #32
+ movls r2, r1, lsr r2
+ movhi r2, #0
+ mov r0, r2
+ mov r1, #0
+ bx lr
+L2:
+ cmp r2, #0
+ rsbne r3, r2, #32
+ movne r3, r1, asl r3
+ movne r1, r1, lsr r2
+ orrne r0, r3, r0, lsr r2
+ bx lr
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/memmove.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/memmove.S new file mode 100644 index 0000000000..d8588d3d98 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/memmove.S @@ -0,0 +1,40 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+# VOID
+# EFIAPI
+# memmove (
+# IN VOID *Destination,
+# IN CONST VOID *Source,
+# IN UINT32 Size
+# );
+ASM_FUNC(memmove)
+ CMP r2, #0
+ BXEQ lr
+ CMP r0, r1
+ BXEQ lr
+ BHI memmove_backward
+
+memmove_forward:
+ LDRB r3, [r1], #1
+ STRB r3, [r0], #1
+ SUBS r2, r2, #1
+ BXEQ lr
+ B memmove_forward
+
+memmove_backward:
+ add r0, r2
+ add r1, r2
+memmove_backward_loop:
+ LDRB r3, [r1, #-1]!
+ STRB r3, [r0, #-1]!
+ SUBS r2, r2, #1
+ BXEQ lr
+ B memmove_backward_loop
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/moddi3.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/moddi3.S new file mode 100644 index 0000000000..e208f8fd28 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/moddi3.S @@ -0,0 +1,38 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+ASM_FUNC(__moddi3)
+ stmfd sp!, {r4, r5, r7, lr}
+ mov r4, r1, asr #31
+ add r7, sp, #8
+ stmfd sp!, {r10, r11}
+ mov r10, r3, asr #31
+ sub sp, sp, #16
+ mov r5, r4
+ mov r11, r10
+ eor r0, r0, r4
+ eor r1, r1, r4
+ eor r2, r2, r10
+ eor r3, r3, r10
+ add ip, sp, #8
+ subs r0, r0, r4
+ sbc r1, r1, r5
+ subs r2, r2, r10
+ sbc r3, r3, r11
+ str ip, [sp, #0]
+ bl ASM_PFX(__udivmoddi4)
+ ldrd r0, [sp, #8]
+ eor r0, r0, r4
+ eor r1, r1, r4
+ subs r0, r0, r4
+ sbc r1, r1, r5
+ sub sp, r7, #16
+ ldmfd sp!, {r10, r11}
+ ldmfd sp!, {r4, r5, r7, pc}
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/modsi3.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/modsi3.S new file mode 100644 index 0000000000..d67f88f717 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/modsi3.S @@ -0,0 +1,19 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+ASM_FUNC(__modsi3)
+ stmfd sp!, {r4, r5, r7, lr}
+ add r7, sp, #8
+ mov r5, r0
+ mov r4, r1
+ bl ASM_PFX(__divsi3)
+ mul r0, r4, r0
+ rsb r0, r0, r5
+ ldmfd sp!, {r4, r5, r7, pc}
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/muldi3.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/muldi3.S new file mode 100644 index 0000000000..6fdc527ecc --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/muldi3.S @@ -0,0 +1,50 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+ASM_FUNC(__muldi3)
+ stmfd sp!, {r4, r5, r6, r7, lr}
+ add r7, sp, #12
+ stmfd sp!, {r8, r10, r11}
+ ldr r11, L4
+ mov r4, r0, lsr #16
+ and r8, r0, r11
+ and ip, r2, r11
+ mul lr, ip, r8
+ mul ip, r4, ip
+ sub sp, sp, #8
+ add r10, ip, lr, lsr #16
+ and ip, r10, r11
+ and lr, lr, r11
+ mov r6, r2, lsr #16
+ str r4, [sp, #4]
+ add r4, lr, ip, asl #16
+ mul ip, r8, r6
+ mov r5, r10, lsr #16
+ add r10, ip, r4, lsr #16
+ and ip, r10, r11
+ and lr, r4, r11
+ add r4, lr, ip, asl #16
+ mul r0, r3, r0
+ add ip, r5, r10, lsr #16
+ ldr r5, [sp, #4]
+ mla r0, r2, r1, r0
+ mla r5, r6, r5, ip
+ mov r10, r4
+ add r11, r0, r5
+ mov r1, r11
+ mov r0, r4
+ sub sp, r7, #24
+ ldmfd sp!, {r8, r10, r11}
+ ldmfd sp!, {r4, r5, r6, r7, pc}
+ .p2align 2
+L5:
+ .align 2
+L4:
+ .long 65535
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/mullu.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/mullu.S new file mode 100644 index 0000000000..a878f3aaf2 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/mullu.S @@ -0,0 +1,38 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+.text
+
+GCC_ASM_EXPORT(__ARM_ll_mullu)
+GCC_ASM_EXPORT(__aeabi_lmul)
+#
+#INT64
+#EFIAPI
+#__aeabi_lmul (
+# IN INT64 Multiplicand
+# IN INT32 Multiplier
+# );
+#
+ASM_PFX(__ARM_ll_mullu):
+ mov r3, #0
+# Make upper part of INT64 Multiplier 0 and use __aeabi_lmul
+
+#
+#INT64
+#EFIAPI
+#__aeabi_lmul (
+# IN INT64 Multiplicand
+# IN INT64 Multiplier
+# );
+#
+ASM_PFX(__aeabi_lmul):
+ stmdb sp!, {lr}
+ mov lr, r0
+ umull r0, ip, r2, lr
+ mla r1, r2, r1, ip
+ mla r1, r3, lr, r1
+ ldmia sp!, {pc}
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/sourcery.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/sourcery.S new file mode 100644 index 0000000000..81459fcfcd --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/sourcery.S @@ -0,0 +1,49 @@ +#------s------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+
+ .text
+ .align 2
+ GCC_ASM_EXPORT(__aeabi_ulcmp)
+
+ASM_PFX(__aeabi_ulcmp):
+ stmfd sp!, {r4, r5, r8}
+ cmp r3, r1
+ mov r8, r0
+ mov r9, r1
+ mov r4, r2
+ mov r5, r3
+ bls L16
+L2:
+ mvn r0, #0
+L1:
+ ldmfd sp!, {r4, r5, r8}
+ bx lr
+L16:
+ beq L17
+L4:
+ cmp r9, r5
+ bhi L7
+ beq L18
+ cmp r8, r4
+L14:
+ cmpeq r9, r5
+ moveq r0, #0
+ beq L1
+ b L1
+L18:
+ cmp r8, r4
+ bls L14
+L7:
+ mov r0, #1
+ b L1
+L17:
+ cmp r2, r0
+ bhi L2
+ b L4
+
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/switch16.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/switch16.S new file mode 100644 index 0000000000..32870878b3 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/switch16.S @@ -0,0 +1,24 @@ +#/** @file
+# Compiler intrinsic for ARM compiler
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+#
+
+#include <AsmMacroLib.h>
+
+.syntax unified
+
+ASM_FUNC(__switch16)
+ ldrh ip, [lr, #-1]
+ cmp r0, ip
+ add r0, lr, r0, lsl #1
+ ldrshcc r0, [r0, #1]
+ add ip, lr, ip, lsl #1
+ ldrshcs r0, [ip, #1]
+ add ip, lr, r0, lsl #1
+ bx ip
+
+
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/switch32.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/switch32.S new file mode 100644 index 0000000000..040d65d6dc --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/switch32.S @@ -0,0 +1,23 @@ +#/** @file
+# Compiler intrinsic for ARM compiler
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+#
+
+#include <AsmMacroLib.h>
+
+.syntax unified
+
+ASM_FUNC(__switch32)
+ ldr ip, [lr, #-1]
+ cmp r0, ip
+ add r0, lr, r0, lsl #2
+ ldrcc r0, [r0, #3]
+ add ip, lr, ip, lsl #2
+ ldrcs r0, [ip, #3]
+ add ip, lr, r0
+ bx ip
+
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/switch8.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/switch8.S new file mode 100644 index 0000000000..08fec9a8a0 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/switch8.S @@ -0,0 +1,21 @@ +#/** @file
+# Compiler intrinsic for ARM compiler
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+#
+
+#include <AsmMacroLib.h>
+
+.syntax unified
+
+ASM_FUNC(__switch8)
+ ldrb ip, [lr, #-1]
+ cmp r0, ip
+ ldrsbcc r0, [lr, r0]
+ ldrsbcs r0, [lr, ip]
+ add ip, lr, r0, lsl #1
+ bx ip
+
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/switchu8.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/switchu8.S new file mode 100644 index 0000000000..a94b368ef9 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/switchu8.S @@ -0,0 +1,21 @@ +#/** @file
+# Compiler intrinsic for ARM compiler
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+#
+
+#include <AsmMacroLib.h>
+
+.syntax unified
+
+ASM_FUNC(__switchu8)
+ ldrb ip,[lr,#-1]
+ cmp r0,ip
+ ldrbcc r0,[lr,r0]
+ ldrbcs r0,[lr,ip]
+ add ip,lr,r0,LSL #1
+ bx ip
+
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/ucmpdi2.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/ucmpdi2.S new file mode 100644 index 0000000000..8d199fb0e2 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/ucmpdi2.S @@ -0,0 +1,30 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+ASM_FUNC(__ucmpdi2)
+ stmfd sp!, {r4, r5, r8, lr}
+ cmp r1, r3
+ mov r8, r0
+ mov r4, r2
+ mov r5, r3
+ bcc L2
+ bhi L4
+ cmp r0, r2
+ bcc L2
+ movls r0, #1
+ bls L8
+ b L4
+L2:
+ mov r0, #0
+ b L8
+L4:
+ mov r0, #2
+L8:
+ ldmfd sp!, {r4, r5, r8, pc}
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/udivdi3.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/udivdi3.S new file mode 100644 index 0000000000..ccb6f6c6c0 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/udivdi3.S @@ -0,0 +1,19 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+ASM_FUNC(__udivdi3)
+ stmfd sp!, {r7, lr}
+ add r7, sp, #0
+ sub sp, sp, #8
+ mov ip, #0
+ str ip, [sp, #0]
+ bl ASM_PFX(__udivmoddi4)
+ sub sp, r7, #0
+ ldmfd sp!, {r7, pc}
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/udivmoddi4.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/udivmoddi4.S new file mode 100644 index 0000000000..edee8fc336 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/udivmoddi4.S @@ -0,0 +1,236 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+ .syntax unified
+
+ASM_FUNC(__udivmoddi4)
+ stmfd sp!, {r4, r5, r6, r7, lr}
+ add r7, sp, #12
+ stmfd sp!, {r10, r11}
+ sub sp, sp, #20
+ stmia sp, {r2-r3}
+ ldr r6, [sp, #48]
+ orrs r2, r2, r3
+ mov r10, r0
+ mov r11, r1
+ beq L2
+ subs ip, r1, #0
+ bne L4
+ cmp r3, #0
+ bne L6
+ cmp r6, #0
+ beq L8
+ mov r1, r2
+ bl ASM_PFX(__umodsi3)
+ mov r1, #0
+ stmia r6, {r0-r1}
+L8:
+ ldr r1, [sp, #0]
+ mov r0, r10
+ b L45
+L6:
+ cmp r6, #0
+ movne r1, #0
+ stmiane r6, {r0-r1}
+ b L2
+L4:
+ ldr r1, [sp, #0]
+ cmp r1, #0
+ bne L12
+ ldr r2, [sp, #4]
+ cmp r2, #0
+ bne L14
+ cmp r6, #0
+ beq L16
+ mov r1, r2
+ mov r0, r11
+ bl ASM_PFX(__umodsi3)
+ mov r1, #0
+ stmia r6, {r0-r1}
+L16:
+ ldr r1, [sp, #4]
+ mov r0, r11
+L45:
+ bl ASM_PFX(__udivsi3)
+L46:
+ mov r10, r0
+ mov r11, #0
+ b L10
+L14:
+ subs r1, r0, #0
+ bne L18
+ cmp r6, #0
+ beq L16
+ ldr r1, [sp, #4]
+ mov r0, r11
+ bl ASM_PFX(__umodsi3)
+ mov r4, r10
+ mov r5, r0
+ stmia r6, {r4-r5}
+ b L16
+L18:
+ sub r3, r2, #1
+ tst r2, r3
+ bne L22
+ cmp r6, #0
+ movne r4, r0
+ andne r5, ip, r3
+ stmiane r6, {r4-r5}
+L24:
+ rsb r3, r2, #0
+ and r3, r2, r3
+ clz r3, r3
+ rsb r3, r3, #31
+ mov r0, ip, lsr r3
+ b L46
+L22:
+ clz r2, r2
+ clz r3, ip
+ rsb r3, r3, r2
+ cmp r3, #30
+ bhi L48
+ rsb r2, r3, #31
+ add lr, r3, #1
+ mov r3, r1, asl r2
+ str r3, [sp, #12]
+ mov r3, r1, lsr lr
+ ldr r0, [sp, #0]
+ mov r5, ip, lsr lr
+ orr r4, r3, ip, asl r2
+ str r0, [sp, #8]
+ b L29
+L12:
+ ldr r3, [sp, #4]
+ cmp r3, #0
+ bne L30
+ sub r3, r1, #1
+ tst r1, r3
+ bne L32
+ cmp r6, #0
+ andne r3, r3, r0
+ movne r2, r3
+ movne r3, #0
+ stmiane r6, {r2-r3}
+L34:
+ cmp r1, #1
+ beq L10
+ rsb r3, r1, #0
+ and r3, r1, r3
+ clz r3, r3
+ rsb r0, r3, #31
+ mov r1, ip, lsr r0
+ rsb r3, r0, #32
+ mov r0, r10, lsr r0
+ orr ip, r0, ip, asl r3
+ str r1, [sp, #12]
+ str ip, [sp, #8]
+ ldrd r10, [sp, #8]
+ b L10
+L32:
+ clz r2, r1
+ clz r3, ip
+ rsb r3, r3, r2
+ rsb r4, r3, #31
+ mov r2, r0, asl r4
+ mvn r1, r3
+ and r2, r2, r1, asr #31
+ add lr, r3, #33
+ str r2, [sp, #8]
+ add r2, r3, #1
+ mov r3, r3, asr #31
+ and r0, r3, r0, asl r1
+ mov r3, r10, lsr r2
+ orr r3, r3, ip, asl r4
+ and r3, r3, r1, asr #31
+ orr r0, r0, r3
+ mov r3, ip, lsr lr
+ str r0, [sp, #12]
+ mov r0, r10, lsr lr
+ and r5, r3, r2, asr #31
+ rsb r3, lr, #31
+ mov r3, r3, asr #31
+ orr r0, r0, ip, asl r1
+ and r3, r3, ip, lsr r2
+ and r0, r0, r2, asr #31
+ orr r4, r3, r0
+ b L29
+L30:
+ clz r2, r3
+ clz r3, ip
+ rsb r3, r3, r2
+ cmp r3, #31
+ bls L37
+L48:
+ cmp r6, #0
+ stmiane r6, {r10-r11}
+ b L2
+L37:
+ rsb r1, r3, #31
+ mov r0, r0, asl r1
+ add lr, r3, #1
+ mov r2, #0
+ str r0, [sp, #12]
+ mov r0, r10, lsr lr
+ str r2, [sp, #8]
+ sub r2, r3, #31
+ and r0, r0, r2, asr #31
+ mov r3, ip, lsr lr
+ orr r4, r0, ip, asl r1
+ and r5, r3, r2, asr #31
+L29:
+ mov ip, #0
+ mov r10, ip
+ b L40
+L41:
+ ldr r1, [sp, #12]
+ ldr r2, [sp, #8]
+ mov r3, r4, lsr #31
+ orr r5, r3, r5, asl #1
+ mov r3, r1, lsr #31
+ orr r4, r3, r4, asl #1
+ mov r3, r2, lsr #31
+ orr r0, r3, r1, asl #1
+ orr r1, ip, r2, asl #1
+ ldmia sp, {r2-r3}
+ str r0, [sp, #12]
+ subs r2, r2, r4
+ sbc r3, r3, r5
+ str r1, [sp, #8]
+ subs r0, r2, #1
+ sbc r1, r3, #0
+ mov r2, r1, asr #31
+ ldmia sp, {r0-r1}
+ mov r3, r2
+ and ip, r2, #1
+ and r3, r3, r1
+ and r2, r2, r0
+ subs r4, r4, r2
+ sbc r5, r5, r3
+ add r10, r10, #1
+L40:
+ cmp r10, lr
+ bne L41
+ ldrd r0, [sp, #8]
+ adds r0, r0, r0
+ adc r1, r1, r1
+ cmp r6, #0
+ orr r10, r0, ip
+ mov r11, r1
+ stmiane r6, {r4-r5}
+ b L10
+L2:
+ mov r10, #0
+ mov r11, #0
+L10:
+ mov r0, r10
+ mov r1, r11
+ sub sp, r7, #20
+ ldmfd sp!, {r10, r11}
+ ldmfd sp!, {r4, r5, r6, r7, pc}
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/udivsi3.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/udivsi3.S new file mode 100644 index 0000000000..100a6a00d8 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/udivsi3.S @@ -0,0 +1,51 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+ .syntax unified
+
+ASM_FUNC(__udivsi3)
+ cmp r1, #0
+ cmpne r0, #0
+ stmfd sp!, {r4, r5, r7, lr}
+ add r7, sp, #8
+ beq L2
+ clz r2, r1
+ clz r3, r0
+ rsb r3, r3, r2
+ cmp r3, #31
+ bhi L2
+ ldmfdeq sp!, {r4, r5, r7, pc}
+ add r5, r3, #1
+ rsb r3, r3, #31
+ mov lr, #0
+ mov r2, r0, asl r3
+ mov ip, r0, lsr r5
+ mov r4, lr
+ b L8
+L9:
+ mov r0, r2, lsr #31
+ orr ip, r0, ip, asl #1
+ orr r2, r3, lr
+ rsb r3, ip, r1
+ sub r3, r3, #1
+ and r0, r1, r3, asr #31
+ mov lr, r3, lsr #31
+ rsb ip, r0, ip
+ add r4, r4, #1
+L8:
+ cmp r4, r5
+ mov r3, r2, asl #1
+ bne L9
+ orr r0, r3, lr
+ ldmfd sp!, {r4, r5, r7, pc}
+L2:
+ mov r0, #0
+ ldmfd sp!, {r4, r5, r7, pc}
+
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/uldiv.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/uldiv.S new file mode 100644 index 0000000000..f61128301a --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/uldiv.S @@ -0,0 +1,261 @@ +//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+
+
+ .text
+ .align 2
+ GCC_ASM_EXPORT(__aeabi_uldivmod)
+
+//
+//UINT64
+//EFIAPI
+//__aeabi_uldivmod (
+// IN UINT64 Dividend
+// IN UINT64 Divisor
+// )
+//
+ASM_PFX(__aeabi_uldivmod):
+ stmdb sp!, {r4, r5, r6, lr}
+ mov r4, r1
+ mov r5, r0
+ mov r6, #0 // 0x0
+ orrs ip, r3, r2, lsr #31
+ bne ASM_PFX(__aeabi_uldivmod_label1)
+ tst r2, r2
+ beq ASM_PFX(_ll_div0)
+ movs ip, r2, lsr #15
+ addeq r6, r6, #16 // 0x10
+ mov ip, r2, lsl r6
+ movs lr, ip, lsr #23
+ moveq ip, ip, lsl #8
+ addeq r6, r6, #8 // 0x8
+ movs lr, ip, lsr #27
+ moveq ip, ip, lsl #4
+ addeq r6, r6, #4 // 0x4
+ movs lr, ip, lsr #29
+ moveq ip, ip, lsl #2
+ addeq r6, r6, #2 // 0x2
+ movs lr, ip, lsr #30
+ moveq ip, ip, lsl #1
+ addeq r6, r6, #1 // 0x1
+ b ASM_PFX(_ll_udiv_small)
+ASM_PFX(__aeabi_uldivmod_label1):
+ tst r3, #-2147483648 // 0x80000000
+ bne ASM_PFX(__aeabi_uldivmod_label2)
+ movs ip, r3, lsr #15
+ addeq r6, r6, #16 // 0x10
+ mov ip, r3, lsl r6
+ movs lr, ip, lsr #23
+ moveq ip, ip, lsl #8
+ addeq r6, r6, #8 // 0x8
+ movs lr, ip, lsr #27
+ moveq ip, ip, lsl #4
+ addeq r6, r6, #4 // 0x4
+ movs lr, ip, lsr #29
+ moveq ip, ip, lsl #2
+ addeq r6, r6, #2 // 0x2
+ movs lr, ip, lsr #30
+ addeq r6, r6, #1 // 0x1
+ rsb r3, r6, #32 // 0x20
+ moveq ip, ip, lsl #1
+ orr ip, ip, r2, lsr r3
+ mov lr, r2, lsl r6
+ b ASM_PFX(_ll_udiv_big)
+ASM_PFX(__aeabi_uldivmod_label2):
+ mov ip, r3
+ mov lr, r2
+ b ASM_PFX(_ll_udiv_ginormous)
+
+ASM_PFX(_ll_udiv_small):
+ cmp r4, ip, lsl #1
+ mov r3, #0 // 0x0
+ subcs r4, r4, ip, lsl #1
+ addcs r3, r3, #2 // 0x2
+ cmp r4, ip
+ subcs r4, r4, ip
+ adcs r3, r3, #0 // 0x0
+ add r2, r6, #32 // 0x20
+ cmp r2, #32 // 0x20
+ rsb ip, ip, #0 // 0x0
+ bcc ASM_PFX(_ll_udiv_small_label1)
+ orrs r0, r4, r5, lsr #30
+ moveq r4, r5
+ moveq r5, #0 // 0x0
+ subeq r2, r2, #32 // 0x20
+ASM_PFX(_ll_udiv_small_label1):
+ mov r1, #0 // 0x0
+ cmp r2, #16 // 0x10
+ bcc ASM_PFX(_ll_udiv_small_label2)
+ movs r0, r4, lsr #14
+ moveq r4, r4, lsl #16
+ addeq r1, r1, #16 // 0x10
+ASM_PFX(_ll_udiv_small_label2):
+ sub lr, r2, r1
+ cmp lr, #8 // 0x8
+ bcc ASM_PFX(_ll_udiv_small_label3)
+ movs r0, r4, lsr #22
+ moveq r4, r4, lsl #8
+ addeq r1, r1, #8 // 0x8
+ASM_PFX(_ll_udiv_small_label3):
+ rsb r0, r1, #32 // 0x20
+ sub r2, r2, r1
+ orr r4, r4, r5, lsr r0
+ mov r5, r5, lsl r1
+ cmp r2, #1 // 0x1
+ bcc ASM_PFX(_ll_udiv_small_label5)
+ sub r2, r2, #1 // 0x1
+ and r0, r2, #7 // 0x7
+ eor r0, r0, #7 // 0x7
+ adds r0, r0, r0, lsl #1
+ add pc, pc, r0, lsl #2
+ nop // (mov r0,r0)
+ASM_PFX(_ll_udiv_small_label4):
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ rsbcc r4, ip, r4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ rsbcc r4, ip, r4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ rsbcc r4, ip, r4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ rsbcc r4, ip, r4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ rsbcc r4, ip, r4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ rsbcc r4, ip, r4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ rsbcc r4, ip, r4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ sub r2, r2, #8 // 0x8
+ tst r2, r2
+ rsbcc r4, ip, r4
+ bpl ASM_PFX(_ll_udiv_small_label4)
+ASM_PFX(_ll_udiv_small_label5):
+ mov r2, r4, lsr r6
+ bic r4, r4, r2, lsl r6
+ adcs r0, r5, r5
+ adc r1, r4, r4
+ add r1, r1, r3, lsl r6
+ mov r3, #0 // 0x0
+ ldmia sp!, {r4, r5, r6, pc}
+
+ASM_PFX(_ll_udiv_big):
+ subs r0, r5, lr
+ mov r3, #0 // 0x0
+ sbcs r1, r4, ip
+ movcs r5, r0
+ movcs r4, r1
+ adcs r3, r3, #0 // 0x0
+ subs r0, r5, lr
+ sbcs r1, r4, ip
+ movcs r5, r0
+ movcs r4, r1
+ adcs r3, r3, #0 // 0x0
+ subs r0, r5, lr
+ sbcs r1, r4, ip
+ movcs r5, r0
+ movcs r4, r1
+ adcs r3, r3, #0 // 0x0
+ mov r1, #0 // 0x0
+ rsbs lr, lr, #0 // 0x0
+ rsc ip, ip, #0 // 0x0
+ cmp r6, #16 // 0x10
+ bcc ASM_PFX(_ll_udiv_big_label1)
+ movs r0, r4, lsr #14
+ moveq r4, r4, lsl #16
+ addeq r1, r1, #16 // 0x10
+ASM_PFX(_ll_udiv_big_label1):
+ sub r2, r6, r1
+ cmp r2, #8 // 0x8
+ bcc ASM_PFX(_ll_udiv_big_label2)
+ movs r0, r4, lsr #22
+ moveq r4, r4, lsl #8
+ addeq r1, r1, #8 // 0x8
+ASM_PFX(_ll_udiv_big_label2):
+ rsb r0, r1, #32 // 0x20
+ sub r2, r6, r1
+ orr r4, r4, r5, lsr r0
+ mov r5, r5, lsl r1
+ cmp r2, #1 // 0x1
+ bcc ASM_PFX(_ll_udiv_big_label4)
+ sub r2, r2, #1 // 0x1
+ and r0, r2, #3 // 0x3
+ rsb r0, r0, #3 // 0x3
+ adds r0, r0, r0, lsl #1
+ add pc, pc, r0, lsl #3
+ nop // (mov r0,r0)
+ASM_PFX(_ll_udiv_big_label3):
+ adcs r5, r5, r5
+ adcs r4, r4, r4
+ adcs r0, lr, r5
+ adcs r1, ip, r4
+ movcs r5, r0
+ movcs r4, r1
+ adcs r5, r5, r5
+ adcs r4, r4, r4
+ adcs r0, lr, r5
+ adcs r1, ip, r4
+ movcs r5, r0
+ movcs r4, r1
+ adcs r5, r5, r5
+ adcs r4, r4, r4
+ adcs r0, lr, r5
+ adcs r1, ip, r4
+ movcs r5, r0
+ movcs r4, r1
+ sub r2, r2, #4 // 0x4
+ adcs r5, r5, r5
+ adcs r4, r4, r4
+ adcs r0, lr, r5
+ adcs r1, ip, r4
+ tst r2, r2
+ movcs r5, r0
+ movcs r4, r1
+ bpl ASM_PFX(_ll_udiv_big_label3)
+ASM_PFX(_ll_udiv_big_label4):
+ mov r1, #0 // 0x0
+ mov r2, r5, lsr r6
+ bic r5, r5, r2, lsl r6
+ adcs r0, r5, r5
+ adc r1, r1, #0 // 0x0
+ movs lr, r3, lsl r6
+ mov r3, r4, lsr r6
+ bic r4, r4, r3, lsl r6
+ adc r1, r1, #0 // 0x0
+ adds r0, r0, lr
+ orr r2, r2, r4, ror r6
+ adc r1, r1, #0 // 0x0
+ ldmia sp!, {r4, r5, r6, pc}
+
+ASM_PFX(_ll_udiv_ginormous):
+ subs r2, r5, lr
+ mov r1, #0 // 0x0
+ sbcs r3, r4, ip
+ adc r0, r1, r1
+ movcc r2, r5
+ movcc r3, r4
+ ldmia sp!, {r4, r5, r6, pc}
+
+ASM_PFX(_ll_div0):
+ ldmia sp!, {r4, r5, r6, lr}
+ mov r0, #0 // 0x0
+ mov r1, #0 // 0x0
+ b ASM_PFX(__aeabi_ldiv0)
+
+ASM_PFX(__aeabi_ldiv0):
+ bx r14
+
+
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/uldiv.asm b/MdePkg/Library/CompilerIntrinsicsLib/Arm/uldiv.asm new file mode 100644 index 0000000000..e143052a71 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/uldiv.asm @@ -0,0 +1,282 @@ +//------------------------------------------------------------------------------
+//
+// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+// Copyright (c) 2018, Pete Batard. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+
+ EXPORT __aeabi_uldivmod
+ EXPORT __rt_udiv64
+
+ AREA s___aeabi_uldivmod, CODE, READONLY, ARM
+
+ ARM
+
+;
+;UINT64
+;EFIAPI
+;__rt_udiv64 (
+; IN UINT64 Divisor
+; IN UINT64 Dividend
+; )
+;
+__rt_udiv64
+ ; Swap r0-r1 and r2-r3
+ mov r12, r0
+ mov r0, r2
+ mov r2, r12
+ mov r12, r1
+ mov r1, r3
+ mov r3, r12
+ b __aeabi_uldivmod
+
+;
+;UINT64
+;EFIAPI
+;__aeabi_uldivmod (
+; IN UINT64 Dividend
+; IN UINT64 Divisor
+; )
+;
+__aeabi_uldivmod
+ stmdb sp!, {r4, r5, r6, lr}
+ mov r4, r1
+ mov r5, r0
+ mov r6, #0 ; 0x0
+ orrs ip, r3, r2, lsr #31
+ bne __aeabi_uldivmod_label1
+ tst r2, r2
+ beq _ll_div0
+ movs ip, r2, lsr #15
+ addeq r6, r6, #16 ; 0x10
+ mov ip, r2, lsl r6
+ movs lr, ip, lsr #23
+ moveq ip, ip, lsl #8
+ addeq r6, r6, #8 ; 0x8
+ movs lr, ip, lsr #27
+ moveq ip, ip, lsl #4
+ addeq r6, r6, #4 ; 0x4
+ movs lr, ip, lsr #29
+ moveq ip, ip, lsl #2
+ addeq r6, r6, #2 ; 0x2
+ movs lr, ip, lsr #30
+ moveq ip, ip, lsl #1
+ addeq r6, r6, #1 ; 0x1
+ b _ll_udiv_small
+__aeabi_uldivmod_label1
+ tst r3, #-2147483648 ; 0x80000000
+ bne __aeabi_uldivmod_label2
+ movs ip, r3, lsr #15
+ addeq r6, r6, #16 ; 0x10
+ mov ip, r3, lsl r6
+ movs lr, ip, lsr #23
+ moveq ip, ip, lsl #8
+ addeq r6, r6, #8 ; 0x8
+ movs lr, ip, lsr #27
+ moveq ip, ip, lsl #4
+ addeq r6, r6, #4 ; 0x4
+ movs lr, ip, lsr #29
+ moveq ip, ip, lsl #2
+ addeq r6, r6, #2 ; 0x2
+ movs lr, ip, lsr #30
+ addeq r6, r6, #1 ; 0x1
+ rsb r3, r6, #32 ; 0x20
+ moveq ip, ip, lsl #1
+ orr ip, ip, r2, lsr r3
+ mov lr, r2, lsl r6
+ b _ll_udiv_big
+__aeabi_uldivmod_label2
+ mov ip, r3
+ mov lr, r2
+ b _ll_udiv_ginormous
+
+_ll_udiv_small
+ cmp r4, ip, lsl #1
+ mov r3, #0 ; 0x0
+ subcs r4, r4, ip, lsl #1
+ addcs r3, r3, #2 ; 0x2
+ cmp r4, ip
+ subcs r4, r4, ip
+ adcs r3, r3, #0 ; 0x0
+ add r2, r6, #32 ; 0x20
+ cmp r2, #32 ; 0x20
+ rsb ip, ip, #0 ; 0x0
+ bcc _ll_udiv_small_label1
+ orrs r0, r4, r5, lsr #30
+ moveq r4, r5
+ moveq r5, #0 ; 0x0
+ subeq r2, r2, #32 ; 0x20
+_ll_udiv_small_label1
+ mov r1, #0 ; 0x0
+ cmp r2, #16 ; 0x10
+ bcc _ll_udiv_small_label2
+ movs r0, r4, lsr #14
+ moveq r4, r4, lsl #16
+ addeq r1, r1, #16 ; 0x10
+_ll_udiv_small_label2
+ sub lr, r2, r1
+ cmp lr, #8 ; 0x8
+ bcc _ll_udiv_small_label3
+ movs r0, r4, lsr #22
+ moveq r4, r4, lsl #8
+ addeq r1, r1, #8 ; 0x8
+_ll_udiv_small_label3
+ rsb r0, r1, #32 ; 0x20
+ sub r2, r2, r1
+ orr r4, r4, r5, lsr r0
+ mov r5, r5, lsl r1
+ cmp r2, #1 ; 0x1
+ bcc _ll_udiv_small_label5
+ sub r2, r2, #1 ; 0x1
+ and r0, r2, #7 ; 0x7
+ eor r0, r0, #7 ; 0x7
+ adds r0, r0, r0, lsl #1
+ add pc, pc, r0, lsl #2
+ nop ; (mov r0,r0)
+_ll_udiv_small_label4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ rsbcc r4, ip, r4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ rsbcc r4, ip, r4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ rsbcc r4, ip, r4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ rsbcc r4, ip, r4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ rsbcc r4, ip, r4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ rsbcc r4, ip, r4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ rsbcc r4, ip, r4
+ adcs r5, r5, r5
+ adcs r4, ip, r4, lsl #1
+ sub r2, r2, #8 ; 0x8
+ tst r2, r2
+ rsbcc r4, ip, r4
+ bpl _ll_udiv_small_label4
+_ll_udiv_small_label5
+ mov r2, r4, lsr r6
+ bic r4, r4, r2, lsl r6
+ adcs r0, r5, r5
+ adc r1, r4, r4
+ add r1, r1, r3, lsl r6
+ mov r3, #0 ; 0x0
+ ldmia sp!, {r4, r5, r6, pc}
+
+_ll_udiv_big
+ subs r0, r5, lr
+ mov r3, #0 ; 0x0
+ sbcs r1, r4, ip
+ movcs r5, r0
+ movcs r4, r1
+ adcs r3, r3, #0 ; 0x0
+ subs r0, r5, lr
+ sbcs r1, r4, ip
+ movcs r5, r0
+ movcs r4, r1
+ adcs r3, r3, #0 ; 0x0
+ subs r0, r5, lr
+ sbcs r1, r4, ip
+ movcs r5, r0
+ movcs r4, r1
+ adcs r3, r3, #0 ; 0x0
+ mov r1, #0 ; 0x0
+ rsbs lr, lr, #0 ; 0x0
+ rsc ip, ip, #0 ; 0x0
+ cmp r6, #16 ; 0x10
+ bcc _ll_udiv_big_label1
+ movs r0, r4, lsr #14
+ moveq r4, r4, lsl #16
+ addeq r1, r1, #16 ; 0x10
+_ll_udiv_big_label1
+ sub r2, r6, r1
+ cmp r2, #8 ; 0x8
+ bcc _ll_udiv_big_label2
+ movs r0, r4, lsr #22
+ moveq r4, r4, lsl #8
+ addeq r1, r1, #8 ; 0x8
+_ll_udiv_big_label2
+ rsb r0, r1, #32 ; 0x20
+ sub r2, r6, r1
+ orr r4, r4, r5, lsr r0
+ mov r5, r5, lsl r1
+ cmp r2, #1 ; 0x1
+ bcc _ll_udiv_big_label4
+ sub r2, r2, #1 ; 0x1
+ and r0, r2, #3 ; 0x3
+ rsb r0, r0, #3 ; 0x3
+ adds r0, r0, r0, lsl #1
+ add pc, pc, r0, lsl #3
+ nop ; (mov r0,r0)
+_ll_udiv_big_label3
+ adcs r5, r5, r5
+ adcs r4, r4, r4
+ adcs r0, lr, r5
+ adcs r1, ip, r4
+ movcs r5, r0
+ movcs r4, r1
+ adcs r5, r5, r5
+ adcs r4, r4, r4
+ adcs r0, lr, r5
+ adcs r1, ip, r4
+ movcs r5, r0
+ movcs r4, r1
+ adcs r5, r5, r5
+ adcs r4, r4, r4
+ adcs r0, lr, r5
+ adcs r1, ip, r4
+ movcs r5, r0
+ movcs r4, r1
+ sub r2, r2, #4 ; 0x4
+ adcs r5, r5, r5
+ adcs r4, r4, r4
+ adcs r0, lr, r5
+ adcs r1, ip, r4
+ tst r2, r2
+ movcs r5, r0
+ movcs r4, r1
+ bpl _ll_udiv_big_label3
+_ll_udiv_big_label4
+ mov r1, #0 ; 0x0
+ mov r2, r5, lsr r6
+ bic r5, r5, r2, lsl r6
+ adcs r0, r5, r5
+ adc r1, r1, #0 ; 0x0
+ movs lr, r3, lsl r6
+ mov r3, r4, lsr r6
+ bic r4, r4, r3, lsl r6
+ adc r1, r1, #0 ; 0x0
+ adds r0, r0, lr
+ orr r2, r2, r4, ror r6
+ adc r1, r1, #0 ; 0x0
+ ldmia sp!, {r4, r5, r6, pc}
+
+_ll_udiv_ginormous
+ subs r2, r5, lr
+ mov r1, #0 ; 0x0
+ sbcs r3, r4, ip
+ adc r0, r1, r1
+ movcc r2, r5
+ movcc r3, r4
+ ldmia sp!, {r4, r5, r6, pc}
+
+_ll_div0
+ ldmia sp!, {r4, r5, r6, lr}
+ mov r0, #0 ; 0x0
+ mov r1, #0 ; 0x0
+ b __aeabi_ldiv0
+
+__aeabi_ldiv0
+ bx r14
+
+ END
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/umoddi3.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/umoddi3.S new file mode 100644 index 0000000000..b22a785e08 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/umoddi3.S @@ -0,0 +1,21 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+ASM_FUNC(__umoddi3)
+ stmfd sp!, {r7, lr}
+ add r7, sp, #0
+ sub sp, sp, #16
+ add ip, sp, #8
+ str ip, [sp, #0]
+ bl ASM_PFX(__udivmoddi4)
+ ldrd r0, [sp, #8]
+ sub sp, r7, #0
+ ldmfd sp!, {r7, pc}
+
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/umodsi3.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/umodsi3.S new file mode 100644 index 0000000000..ee548afe17 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/umodsi3.S @@ -0,0 +1,20 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+ASM_FUNC(__umodsi3)
+ stmfd sp!, {r4, r5, r7, lr}
+ add r7, sp, #8
+ mov r5, r0
+ mov r4, r1
+ bl ASM_PFX(__udivsi3)
+ mul r0, r4, r0
+ rsb r0, r0, r5
+ ldmfd sp!, {r4, r5, r7, pc}
+
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/uread.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/uread.S new file mode 100644 index 0000000000..132975c6a1 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/uread.S @@ -0,0 +1,54 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+#
+#UINT32
+#EFIAPI
+#__aeabi_uread4 (
+# IN VOID *Pointer
+# );
+#
+ASM_FUNC(__aeabi_uread4)
+ ldrb r1, [r0]
+ ldrb r2, [r0, #1]
+ ldrb r3, [r0, #2]
+ ldrb r0, [r0, #3]
+ orr r1, r1, r2, lsl #8
+ orr r1, r1, r3, lsl #16
+ orr r0, r1, r0, lsl #24
+ bx lr
+
+#
+#UINT64
+#EFIAPI
+#__aeabi_uread8 (
+# IN VOID *Pointer
+# );
+#
+ASM_FUNC(__aeabi_uread8)
+ mov r3, r0
+
+ ldrb r1, [r3]
+ ldrb r2, [r3, #1]
+ orr r1, r1, r2, lsl #8
+ ldrb r2, [r3, #2]
+ orr r1, r1, r2, lsl #16
+ ldrb r0, [r3, #3]
+ orr r0, r1, r0, lsl #24
+
+ ldrb r1, [r3, #4]
+ ldrb r2, [r3, #5]
+ orr r1, r1, r2, lsl #8
+ ldrb r2, [r3, #6]
+ orr r1, r1, r2, lsl #16
+ ldrb r2, [r3, #7]
+ orr r1, r1, r2, lsl #24
+
+ bx lr
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/Arm/uwrite.S b/MdePkg/Library/CompilerIntrinsicsLib/Arm/uwrite.S new file mode 100644 index 0000000000..2c56ba3e06 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/Arm/uwrite.S @@ -0,0 +1,53 @@ +#------------------------------------------------------------------------------
+#
+# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroLib.h>
+
+#
+#UINT32
+#EFIAPI
+#__aeabi_uwrite4 (
+# IN UINT32 Data,
+# IN VOID *Pointer
+# );
+#
+ASM_FUNC(__aeabi_uwrite4)
+ mov r2, r0, lsr #8
+ strb r0, [r1]
+ strb r2, [r1, #1]
+ mov r2, r0, lsr #16
+ strb r2, [r1, #2]
+ mov r2, r0, lsr #24
+ strb r2, [r1, #3]
+ bx lr
+
+#
+#UINT64
+#EFIAPI
+#__aeabi_uwrite8 (
+# IN UINT64 Data,
+# IN VOID *Pointer
+# );
+#
+ASM_FUNC(__aeabi_uwrite8)
+ mov r3, r0, lsr #8
+ strb r0, [r2]
+ strb r3, [r2, #1]
+ mov r3, r0, lsr #16
+ strb r3, [r2, #2]
+ mov r3, r0, lsr #24
+ strb r3, [r2, #3]
+
+ mov r3, r1, lsr #8
+ strb r1, [r2, #4]
+ strb r3, [r2, #5]
+ mov r3, r1, lsr #16
+ strb r3, [r2, #6]
+ mov r3, r1, lsr #24
+ strb r3, [r2, #7]
+ bx lr
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf b/MdePkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf new file mode 100644 index 0000000000..ac48b46246 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf @@ -0,0 +1,76 @@ +#/** @file
+# Base Library implementation.
+#
+# Copyright (c) 2009, Apple Inc. All rights reserved.<BR>
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 1.29
+ BASE_NAME = CompilerIntrinsicsLib
+ FILE_GUID = 2A6B451F-B99D-47B1-8F29-D805433C62E0
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = CompilerIntrinsicsLib
+
+[Sources]
+ memcpy.c | GCC
+ memset.c | GCC
+
+ memcpy_ms.c | MSFT
+ memset_ms.c | MSFT
+ memcmp_ms.c | MSFT
+ memmove_ms.c | MSFT
+
+[Sources.ARM]
+ Arm/ashrdi3.S | GCC
+ Arm/ashldi3.S | GCC
+ Arm/div.S | GCC
+ Arm/divdi3.S | GCC
+ Arm/divsi3.S | GCC
+ Arm/lshrdi3.S | GCC
+ Arm/memmove.S | GCC
+ Arm/modsi3.S | GCC
+ Arm/moddi3.S | GCC
+ Arm/muldi3.S | GCC
+ Arm/mullu.S | GCC
+ Arm/udivsi3.S | GCC
+ Arm/umodsi3.S | GCC
+ Arm/udivdi3.S | GCC
+ Arm/umoddi3.S | GCC
+ Arm/udivmoddi4.S | GCC
+ Arm/clzsi2.S | GCC
+ Arm/ctzsi2.S | GCC
+ Arm/ucmpdi2.S | GCC
+ Arm/switch8.S | GCC
+ Arm/switchu8.S | GCC
+ Arm/switch16.S | GCC
+ Arm/switch32.S | GCC
+ Arm/sourcery.S | GCC
+ Arm/uldiv.S | GCC
+ Arm/ldivmod.S | GCC
+ Arm/lasr.S | GCC
+ Arm/llsr.S | GCC
+ Arm/llsl.S | GCC
+ Arm/uread.S | GCC
+ Arm/uwrite.S | GCC
+
+ Arm/div.asm | MSFT
+ Arm/uldiv.asm | MSFT
+ Arm/ldivmod.asm | MSFT
+ Arm/llsr.asm | MSFT
+
+[Sources.AARCH64]
+ AArch64/Atomics.S | GCC
+ AArch64/ashlti3.S | GCC
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[BuildOptions]
+ MSFT:*_*_*_CC_FLAGS = /GL-
+ MSFT:*_*_ARM_ASM_FLAGS = /oldit
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/memcmp_ms.c b/MdePkg/Library/CompilerIntrinsicsLib/memcmp_ms.c new file mode 100644 index 0000000000..cedbfca471 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/memcmp_ms.c @@ -0,0 +1,48 @@ +// ------------------------------------------------------------------------------
+//
+// Copyright (c) 2019, Pete Batard. All rights reserved.
+// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// ------------------------------------------------------------------------------
+
+#if defined (_M_ARM64)
+typedef unsigned __int64 size_t;
+#else
+typedef unsigned __int32 size_t;
+#endif
+
+int
+memcmp (
+ void *,
+ void *,
+ size_t
+ );
+
+#pragma intrinsic(memcmp)
+#pragma function(memcmp)
+int
+memcmp (
+ const void *s1,
+ const void *s2,
+ size_t n
+ )
+{
+ unsigned char const *t1;
+ unsigned char const *t2;
+
+ t1 = s1;
+ t2 = s2;
+
+ while (n-- != 0) {
+ if (*t1 != *t2) {
+ return (int)*t1 - (int)*t2;
+ }
+
+ t1++;
+ t2++;
+ }
+
+ return 0;
+}
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/memcpy.c b/MdePkg/Library/CompilerIntrinsicsLib/memcpy.c new file mode 100644 index 0000000000..415146f7f2 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/memcpy.c @@ -0,0 +1,67 @@ +// ------------------------------------------------------------------------------
+//
+// Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// ------------------------------------------------------------------------------
+
+typedef __SIZE_TYPE__ size_t;
+
+static void
+__memcpy (
+ void *dest,
+ const void *src,
+ size_t n
+ )
+{
+ unsigned char *d;
+ unsigned char const *s;
+
+ d = dest;
+ s = src;
+
+ while (n-- != 0) {
+ *d++ = *s++;
+ }
+}
+
+void *
+memcpy (
+ void *dest,
+ const void *src,
+ size_t n
+ )
+{
+ __memcpy (dest, src, n);
+ return dest;
+}
+
+#ifdef __arm__
+
+__attribute__ ((__alias__ ("__memcpy")))
+void
+__aeabi_memcpy (
+ void *dest,
+ const void *src,
+ size_t n
+ );
+
+__attribute__ ((__alias__ ("__memcpy")))
+void
+__aeabi_memcpy4 (
+ void *dest,
+ const void *src,
+ size_t n
+ );
+
+__attribute__ ((__alias__ ("__memcpy")))
+void
+__aeabi_memcpy8 (
+ void *dest,
+ const void *src,
+ size_t n
+ );
+
+#endif
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/memcpy_ms.c b/MdePkg/Library/CompilerIntrinsicsLib/memcpy_ms.c new file mode 100644 index 0000000000..0eafa83ed4 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/memcpy_ms.c @@ -0,0 +1,43 @@ +// ------------------------------------------------------------------------------
+//
+// Copyright (c) 2017, Pete Batard. All rights reserved.<BR>
+// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// ------------------------------------------------------------------------------
+
+#if defined (_M_ARM64)
+typedef unsigned __int64 size_t;
+#else
+typedef unsigned __int32 size_t;
+#endif
+
+void *
+memcpy (
+ void *,
+ const void *,
+ size_t
+ );
+
+#pragma intrinsic(memcpy)
+#pragma function(memcpy)
+void *
+memcpy (
+ void *dest,
+ const void *src,
+ size_t n
+ )
+{
+ unsigned char *d;
+ unsigned char const *s;
+
+ d = dest;
+ s = src;
+
+ while (n-- != 0) {
+ *d++ = *s++;
+ }
+
+ return dest;
+}
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/memmove_ms.c b/MdePkg/Library/CompilerIntrinsicsLib/memmove_ms.c new file mode 100644 index 0000000000..f68eb52a6c --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/memmove_ms.c @@ -0,0 +1,51 @@ +// ------------------------------------------------------------------------------
+//
+// Copyright (c) 2019, Pete Batard. All rights reserved.
+// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// ------------------------------------------------------------------------------
+
+#if defined (_M_ARM64)
+typedef unsigned __int64 size_t;
+#else
+typedef unsigned __int32 size_t;
+#endif
+
+void *
+memmove (
+ void *,
+ const void *,
+ size_t
+ );
+
+#pragma intrinsic(memmove)
+#pragma function(memmove)
+void *
+memmove (
+ void *dest,
+ const void *src,
+ size_t n
+ )
+{
+ unsigned char *d;
+ unsigned char const *s;
+
+ d = dest;
+ s = src;
+
+ if (d < s) {
+ while (n-- != 0) {
+ *d++ = *s++;
+ }
+ } else {
+ d += n;
+ s += n;
+ while (n-- != 0) {
+ *--d = *--s;
+ }
+ }
+
+ return dest;
+}
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/memset.c b/MdePkg/Library/CompilerIntrinsicsLib/memset.c new file mode 100644 index 0000000000..3e45302fe6 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/memset.c @@ -0,0 +1,96 @@ +// ------------------------------------------------------------------------------
+//
+// Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
+// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// ------------------------------------------------------------------------------
+
+typedef __SIZE_TYPE__ size_t;
+
+static __attribute__ ((__used__))
+void *
+__memset (
+ void *s,
+ int c,
+ size_t n
+ )
+{
+ unsigned char *d;
+
+ d = s;
+
+ while (n-- != 0) {
+ *d++ = c;
+ }
+
+ return s;
+}
+
+//
+// Other modules (such as CryptoPkg/IntrinsicLib) may provide another
+// implementation of memset(), which may conflict with this one if this
+// object was pulled into the link due to the definitions below. So make
+// our memset() 'weak' to let the other implementation take precedence.
+//
+__attribute__ ((__weak__, __alias__ ("__memset")))
+void *
+memset (
+ void *dest,
+ int c,
+ size_t n
+ );
+
+#ifdef __arm__
+
+void
+__aeabi_memset (
+ void *dest,
+ size_t n,
+ int c
+ )
+{
+ __memset (dest, c, n);
+}
+
+__attribute__ ((__alias__ ("__aeabi_memset")))
+void
+__aeabi_memset4 (
+ void *dest,
+ size_t n,
+ int c
+ );
+
+__attribute__ ((__alias__ ("__aeabi_memset")))
+void
+__aeabi_memset8 (
+ void *dest,
+ size_t n,
+ int c
+ );
+
+void
+__aeabi_memclr (
+ void *dest,
+ size_t n
+ )
+{
+ __memset (dest, 0, n);
+}
+
+__attribute__ ((__alias__ ("__aeabi_memclr")))
+void
+__aeabi_memclr4 (
+ void *dest,
+ size_t n
+ );
+
+__attribute__ ((__alias__ ("__aeabi_memclr")))
+void
+__aeabi_memclr8 (
+ void *dest,
+ size_t n
+ );
+
+#endif
diff --git a/MdePkg/Library/CompilerIntrinsicsLib/memset_ms.c b/MdePkg/Library/CompilerIntrinsicsLib/memset_ms.c new file mode 100644 index 0000000000..5882cd28b0 --- /dev/null +++ b/MdePkg/Library/CompilerIntrinsicsLib/memset_ms.c @@ -0,0 +1,41 @@ +// ------------------------------------------------------------------------------
+//
+// Copyright (c) 2017, Pete Batard. All rights reserved.<BR>
+// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// ------------------------------------------------------------------------------
+
+#if defined (_M_ARM64)
+typedef unsigned __int64 size_t;
+#else
+typedef unsigned __int32 size_t;
+#endif
+
+void *
+memset (
+ void *,
+ int,
+ size_t
+ );
+
+#pragma intrinsic(memset)
+#pragma function(memset)
+void *
+memset (
+ void *s,
+ int c,
+ size_t n
+ )
+{
+ unsigned char *d;
+
+ d = s;
+
+ while (n-- != 0) {
+ *d++ = (unsigned char)c;
+ }
+
+ return s;
+}
diff --git a/MdePkg/MdeLibs.dsc.inc b/MdePkg/MdeLibs.dsc.inc index a8c8f4ef36..e40ff7d95e 100644 --- a/MdePkg/MdeLibs.dsc.inc +++ b/MdePkg/MdeLibs.dsc.inc @@ -20,3 +20,13 @@ SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
MmUnblockMemoryLib|MdePkg/Library/MmUnblockMemoryLib/MmUnblockMemoryLibNull.inf
+
+[LibraryClasses.ARM, LibraryClasses.AARCH64]
+ #
+ # It is not possible to prevent the ARM/AARCH64 compilers from inserting generic intrinsic functions.
+ # This library provides the intrinsic functions generated by these compilers.
+ #
+ # Linking this here as a null library will cause all ARM/AARCH64 files to link against it and have
+ # definitions for the intrinsic functions.
+ #
+ NULL|MdePkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc index 109224c527..ebcd79864d 100644 --- a/MdePkg/MdePkg.dsc +++ b/MdePkg/MdePkg.dsc @@ -194,6 +194,7 @@ [Components.ARM, Components.AARCH64]
MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf
MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+ MdePkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
[Components.RISCV64]
MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
|