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| author | Tom Lendacky <thomas.lendacky@amd.com> | 2020-11-06 11:53:03 -0600 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-11-10 19:07:55 +0000 |
| commit | 990ab937c20cd2674e3e2697729f4530dfbabb92 (patch) | |
| tree | 2bfc5a0cb7bf28ca9e5fb5c65cc43f1e646d2507 /MdePkg | |
| parent | 8c610e6075f2a200400970698a810a57ad49220e (diff) | |
| download | edk2-990ab937c20cd2674e3e2697729f4530dfbabb92.tar.gz edk2-990ab937c20cd2674e3e2697729f4530dfbabb92.tar.bz2 edk2-990ab937c20cd2674e3e2697729f4530dfbabb92.zip | |
MdePkg: Clean up GHCB field offsets and save area
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3008
Use OFFSET_OF () and sizeof () to calculate the GHCB register field
offsets instead of hardcoding the values in the GHCB_REGISTER enum.
Define only fields that are used per the GHCB specification, which will
result in removing some fields and adding others.
Also, remove the DR7 field from the GHCB_SAVE_AREA structure since it is
not used/defined in the GHCB specification and then rename the reserved
fields as appropriate.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <5e9245c7600b9b2d55dd7586b8df28b91b75b72b.1604685192.git.thomas.lendacky@amd.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Diffstat (limited to 'MdePkg')
| -rw-r--r-- | MdePkg/Include/Register/Amd/Ghcb.h | 43 |
1 files changed, 17 insertions, 26 deletions
diff --git a/MdePkg/Include/Register/Amd/Ghcb.h b/MdePkg/Include/Register/Amd/Ghcb.h index 54a80da0f6..ccdb662af7 100644 --- a/MdePkg/Include/Register/Amd/Ghcb.h +++ b/MdePkg/Include/Register/Amd/Ghcb.h @@ -82,35 +82,10 @@ #define IOIO_SEG_DS (BIT11 | BIT10)
-typedef enum {
- GhcbCpl = 25,
- GhcbRflags = 46,
- GhcbRip,
- GhcbRsp = 59,
- GhcbRax = 63,
- GhcbRcx = 97,
- GhcbRdx,
- GhcbRbx,
- GhcbRbp = 101,
- GhcbRsi,
- GhcbRdi,
- GhcbR8,
- GhcbR9,
- GhcbR10,
- GhcbR11,
- GhcbR12,
- GhcbR13,
- GhcbR14,
- GhcbR15,
- GhcbXCr0 = 125,
-} GHCB_REGISTER;
-
typedef PACKED struct {
UINT8 Reserved1[203];
UINT8 Cpl;
- UINT8 Reserved2[148];
- UINT64 Dr7;
- UINT8 Reserved3[144];
+ UINT8 Reserved8[300];
UINT64 Rax;
UINT8 Reserved4[264];
UINT64 Rcx;
@@ -136,6 +111,22 @@ typedef PACKED struct { UINT32 GhcbUsage;
} GHCB;
+#define GHCB_SAVE_AREA_QWORD_OFFSET(RegisterField) \
+ (OFFSET_OF (GHCB, SaveArea.RegisterField) / sizeof (UINT64))
+
+typedef enum {
+ GhcbCpl = GHCB_SAVE_AREA_QWORD_OFFSET (Cpl),
+ GhcbRax = GHCB_SAVE_AREA_QWORD_OFFSET (Rax),
+ GhcbRbx = GHCB_SAVE_AREA_QWORD_OFFSET (Rbx),
+ GhcbRcx = GHCB_SAVE_AREA_QWORD_OFFSET (Rcx),
+ GhcbRdx = GHCB_SAVE_AREA_QWORD_OFFSET (Rdx),
+ GhcbXCr0 = GHCB_SAVE_AREA_QWORD_OFFSET (XCr0),
+ GhcbSwExitCode = GHCB_SAVE_AREA_QWORD_OFFSET (SwExitCode),
+ GhcbSwExitInfo1 = GHCB_SAVE_AREA_QWORD_OFFSET (SwExitInfo1),
+ GhcbSwExitInfo2 = GHCB_SAVE_AREA_QWORD_OFFSET (SwExitInfo2),
+ GhcbSwScratch = GHCB_SAVE_AREA_QWORD_OFFSET (SwScratch),
+} GHCB_REGISTER;
+
typedef union {
struct {
UINT32 Lower32Bits;
|