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| author | Pierre Gondois <pierre.gondois@arm.com> | 2023-11-02 13:53:54 +0100 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2024-08-01 13:41:01 +0000 |
| commit | a72d93e1631852b19e2a996fa5fa81109d5c25f4 (patch) | |
| tree | 40ee4242affeb773e33e646d1f0dfff6b03f0aca /MdePkg | |
| parent | 71b9bda1ace32a479d471f26b0e516d0618053bc (diff) | |
| download | edk2-a72d93e1631852b19e2a996fa5fa81109d5c25f4.tar.gz edk2-a72d93e1631852b19e2a996fa5fa81109d5c25f4.tar.bz2 edk2-a72d93e1631852b19e2a996fa5fa81109d5c25f4.zip | |
MdePkg/BaseLib: AARCH64: Add ArmReadCntPctReg()
To enable AARCH64 native instruction support for Openssl,
some interfaces must be implemented. OPENSSL_rdtsc() requests
an access to a counter to get some non-trusted entropy.
Add ArmReadCntPctReg() to read system count.
A similar ArmReadCntPct() function is available in the ArmPkg,
but the CryptoPkg where OPENSSL_rdtsc will reside cannot rely
on the ArmPkg.
Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
Diffstat (limited to 'MdePkg')
| -rw-r--r-- | MdePkg/Include/Library/BaseLib.h | 15 | ||||
| -rw-r--r-- | MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.S | 30 | ||||
| -rw-r--r-- | MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.asm | 30 | ||||
| -rw-r--r-- | MdePkg/Library/BaseLib/BaseLib.inf | 4 |
4 files changed, 78 insertions, 1 deletions
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index 95f805599d..024608fe4b 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -7,6 +7,7 @@ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> Copyright (c) Microsoft Corporation.<BR>
Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+Copyright (c) 2023 - 2024, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -126,6 +127,20 @@ typedef struct { #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+/**
+ Reads the current value of CNTPCT_EL0 register.
+
+ Reads and returns the current value of CNTPCT_EL0.
+ This function is only available on AARCH64.
+
+ @return The current value of CNTPCT_EL0
+**/
+UINT64
+EFIAPI
+ArmReadCntPctReg (
+ VOID
+ );
+
#endif // defined (MDE_CPU_AARCH64)
#if defined (MDE_CPU_RISCV64)
diff --git a/MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.S b/MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.S new file mode 100644 index 0000000000..cfabd7ad8f --- /dev/null +++ b/MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.S @@ -0,0 +1,30 @@ +#------------------------------------------------------------------------------
+#
+# ArmReadCntPctReg() for AArch64
+#
+# Copyright (c) 2023 - 2024, Arm Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+.text
+.p2align 2
+GCC_ASM_EXPORT(ArmReadCntPctReg)
+
+#/**
+# Reads the CNTPCT_EL0 Register.
+#
+# @return The contents of the CNTPCT_EL0 register.
+#
+#**/
+#UINT64
+#EFIAPI
+#ArmReadCntPctReg (
+# VOID
+# );
+#
+ASM_PFX(ArmReadCntPctReg):
+ AARCH64_BTI(c)
+ mrs x0, cntpct_el0
+ ret
diff --git a/MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.asm b/MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.asm new file mode 100644 index 0000000000..98823fdd5e --- /dev/null +++ b/MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.asm @@ -0,0 +1,30 @@ +;------------------------------------------------------------------------------
+;
+; ArmReadCntPctReg() for AArch64
+;
+; Copyright (c) 2023 - 2024, Arm Limited. All rights reserved.<BR>
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+ EXPORT ArmReadCntPctReg
+ AREA BaseLib_LowLevel, CODE, READONLY
+
+;/**
+; Reads the CNTPCT_EL0 Register.
+;
+; @return The contents of the CNTPCT_EL0 register.
+;
+;**/
+;UINT64
+;EFIAPI
+;ArmReadCntPctReg (
+; VOID
+; );
+;
+ArmReadCntPctReg
+ mrs x0, cntpct_el0
+ ret
+
+ END
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index 26e66a8d67..96fc722a07 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -3,7 +3,7 @@ #
# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2024, Arm Limited. All rights reserved.<BR>
# Copyright (c) 2020 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -378,6 +378,7 @@ AArch64/SetJumpLongJump.S | GCC
AArch64/CpuBreakpoint.S | GCC
AArch64/SpeculationBarrier.S | GCC
+ AArch64/ArmReadCntPctReg.S | GCC
AArch64/MemoryFence.asm | MSFT
AArch64/SwitchStack.asm | MSFT
@@ -387,6 +388,7 @@ AArch64/SetJumpLongJump.asm | MSFT
AArch64/CpuBreakpoint.asm | MSFT
AArch64/SpeculationBarrier.asm | MSFT
+ AArch64/ArmReadCntPctReg.asm | MSFT
[Sources.RISCV64]
Math64.c
|